dt-bindings/memory/mt8183-larb-port.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2018 MediaTek Inc.
0004  * Author: Yong Wu <yong.wu@mediatek.com>
0005  */
0006 #ifndef _DT_BINDINGS_MEMORY_MT8183_LARB_PORT_H_
0007 #define _DT_BINDINGS_MEMORY_MT8183_LARB_PORT_H_
0008
0009 #include <dt-bindings/memory/mtk-memory-port.h>
0010
0011 #define M4U_LARB0_ID            0
0012 #define M4U_LARB1_ID            1
0013 #define M4U_LARB2_ID            2
0014 #define M4U_LARB3_ID            3
0015 #define M4U_LARB4_ID            4
0016 #define M4U_LARB5_ID            5
0017 #define M4U_LARB6_ID            6
0018 #define M4U_LARB7_ID            7
0019
0020 /* larb0 */
0021 #define M4U_PORT_DISP_OVL0      MTK_M4U_ID(M4U_LARB0_ID, 0)
0022 #define M4U_PORT_DISP_2L_OVL0_LARB0     MTK_M4U_ID(M4U_LARB0_ID, 1)
0023 #define M4U_PORT_DISP_2L_OVL1_LARB0     MTK_M4U_ID(M4U_LARB0_ID, 2)
0024 #define M4U_PORT_DISP_RDMA0     MTK_M4U_ID(M4U_LARB0_ID, 3)
0025 #define M4U_PORT_DISP_RDMA1     MTK_M4U_ID(M4U_LARB0_ID, 4)
0026 #define M4U_PORT_DISP_WDMA0     MTK_M4U_ID(M4U_LARB0_ID, 5)
0027 #define M4U_PORT_MDP_RDMA0      MTK_M4U_ID(M4U_LARB0_ID, 6)
0028 #define M4U_PORT_MDP_WROT0      MTK_M4U_ID(M4U_LARB0_ID, 7)
0029 #define M4U_PORT_MDP_WDMA0      MTK_M4U_ID(M4U_LARB0_ID, 8)
0030 #define M4U_PORT_DISP_FAKE0     MTK_M4U_ID(M4U_LARB0_ID, 9)
0031
0032 /* larb1 */
0033 #define M4U_PORT_HW_VDEC_MC_EXT     MTK_M4U_ID(M4U_LARB1_ID, 0)
0034 #define M4U_PORT_HW_VDEC_PP_EXT         MTK_M4U_ID(M4U_LARB1_ID, 1)
0035 #define M4U_PORT_HW_VDEC_VLD_EXT    MTK_M4U_ID(M4U_LARB1_ID, 2)
0036 #define M4U_PORT_HW_VDEC_AVC_MV_EXT     MTK_M4U_ID(M4U_LARB1_ID, 3)
0037 #define M4U_PORT_HW_VDEC_PRED_RD_EXT    MTK_M4U_ID(M4U_LARB1_ID, 4)
0038 #define M4U_PORT_HW_VDEC_PRED_WR_EXT    MTK_M4U_ID(M4U_LARB1_ID, 5)
0039 #define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB1_ID, 6)
0040
0041 /* larb2 VPU0 */
0042 #define M4U_PORT_IMG_IPUO       MTK_M4U_ID(M4U_LARB2_ID, 0)
0043 #define M4U_PORT_IMG_IPU3O      MTK_M4U_ID(M4U_LARB2_ID, 1)
0044 #define M4U_PORT_IMG_IPUI       MTK_M4U_ID(M4U_LARB2_ID, 2)
0045
0046 /* larb3 VPU1 */
0047 #define M4U_PORT_CAM_IPUO       MTK_M4U_ID(M4U_LARB3_ID, 0)
0048 #define M4U_PORT_CAM_IPU2O      MTK_M4U_ID(M4U_LARB3_ID, 1)
0049 #define M4U_PORT_CAM_IPU3O      MTK_M4U_ID(M4U_LARB3_ID, 2)
0050 #define M4U_PORT_CAM_IPUI       MTK_M4U_ID(M4U_LARB3_ID, 3)
0051 #define M4U_PORT_CAM_IPU2I      MTK_M4U_ID(M4U_LARB3_ID, 4)
0052
0053 /* larb4 */
0054 #define M4U_PORT_VENC_RCPU      MTK_M4U_ID(M4U_LARB4_ID, 0)
0055 #define M4U_PORT_VENC_REC       MTK_M4U_ID(M4U_LARB4_ID, 1)
0056 #define M4U_PORT_VENC_BSDMA     MTK_M4U_ID(M4U_LARB4_ID, 2)
0057 #define M4U_PORT_VENC_SV_COMV       MTK_M4U_ID(M4U_LARB4_ID, 3)
0058 #define M4U_PORT_VENC_RD_COMV       MTK_M4U_ID(M4U_LARB4_ID, 4)
0059 #define M4U_PORT_JPGENC_RDMA        MTK_M4U_ID(M4U_LARB4_ID, 5)
0060 #define M4U_PORT_JPGENC_BSDMA       MTK_M4U_ID(M4U_LARB4_ID, 6)
0061 #define M4U_PORT_VENC_CUR_LUMA      MTK_M4U_ID(M4U_LARB4_ID, 7)
0062 #define M4U_PORT_VENC_CUR_CHROMA    MTK_M4U_ID(M4U_LARB4_ID, 8)
0063 #define M4U_PORT_VENC_REF_LUMA      MTK_M4U_ID(M4U_LARB4_ID, 9)
0064 #define M4U_PORT_VENC_REF_CHROMA    MTK_M4U_ID(M4U_LARB4_ID, 10)
0065
0066 /* larb5 */
0067 #define M4U_PORT_CAM_IMGI       MTK_M4U_ID(M4U_LARB5_ID, 0)
0068 #define M4U_PORT_CAM_IMG2O      MTK_M4U_ID(M4U_LARB5_ID, 1)
0069 #define M4U_PORT_CAM_IMG3O      MTK_M4U_ID(M4U_LARB5_ID, 2)
0070 #define M4U_PORT_CAM_VIPI       MTK_M4U_ID(M4U_LARB5_ID, 3)
0071 #define M4U_PORT_CAM_LCEI       MTK_M4U_ID(M4U_LARB5_ID, 4)
0072 #define M4U_PORT_CAM_SMXI       MTK_M4U_ID(M4U_LARB5_ID, 5)
0073 #define M4U_PORT_CAM_SMXO       MTK_M4U_ID(M4U_LARB5_ID, 6)
0074 #define M4U_PORT_CAM_WPE0_RDMA1     MTK_M4U_ID(M4U_LARB5_ID, 7)
0075 #define M4U_PORT_CAM_WPE0_RDMA0     MTK_M4U_ID(M4U_LARB5_ID, 8)
0076 #define M4U_PORT_CAM_WPE0_WDMA      MTK_M4U_ID(M4U_LARB5_ID, 9)
0077 #define M4U_PORT_CAM_FDVT_RP        MTK_M4U_ID(M4U_LARB5_ID, 10)
0078 #define M4U_PORT_CAM_FDVT_WR        MTK_M4U_ID(M4U_LARB5_ID, 11)
0079 #define M4U_PORT_CAM_FDVT_RB        MTK_M4U_ID(M4U_LARB5_ID, 12)
0080 #define M4U_PORT_CAM_WPE1_RDMA0     MTK_M4U_ID(M4U_LARB5_ID, 13)
0081 #define M4U_PORT_CAM_WPE1_RDMA1     MTK_M4U_ID(M4U_LARB5_ID, 14)
0082 #define M4U_PORT_CAM_WPE1_WDMA      MTK_M4U_ID(M4U_LARB5_ID, 15)
0083 #define M4U_PORT_CAM_DPE_RDMA       MTK_M4U_ID(M4U_LARB5_ID, 16)
0084 #define M4U_PORT_CAM_DPE_WDMA       MTK_M4U_ID(M4U_LARB5_ID, 17)
0085 #define M4U_PORT_CAM_MFB_RDMA0      MTK_M4U_ID(M4U_LARB5_ID, 18)
0086 #define M4U_PORT_CAM_MFB_RDMA1      MTK_M4U_ID(M4U_LARB5_ID, 19)
0087 #define M4U_PORT_CAM_MFB_WDMA       MTK_M4U_ID(M4U_LARB5_ID, 20)
0088 #define M4U_PORT_CAM_RSC_RDMA0      MTK_M4U_ID(M4U_LARB5_ID, 21)
0089 #define M4U_PORT_CAM_RSC_WDMA       MTK_M4U_ID(M4U_LARB5_ID, 22)
0090 #define M4U_PORT_CAM_OWE_RDMA       MTK_M4U_ID(M4U_LARB5_ID, 23)
0091 #define M4U_PORT_CAM_OWE_WDMA       MTK_M4U_ID(M4U_LARB5_ID, 24)
0092
0093 /* larb6 */
0094 #define M4U_PORT_CAM_IMGO       MTK_M4U_ID(M4U_LARB6_ID, 0)
0095 #define M4U_PORT_CAM_RRZO       MTK_M4U_ID(M4U_LARB6_ID, 1)
0096 #define M4U_PORT_CAM_AAO        MTK_M4U_ID(M4U_LARB6_ID, 2)
0097 #define M4U_PORT_CAM_AFO        MTK_M4U_ID(M4U_LARB6_ID, 3)
0098 #define M4U_PORT_CAM_LSCI0      MTK_M4U_ID(M4U_LARB6_ID, 4)
0099 #define M4U_PORT_CAM_LSCI1      MTK_M4U_ID(M4U_LARB6_ID, 5)
0100 #define M4U_PORT_CAM_PDO        MTK_M4U_ID(M4U_LARB6_ID, 6)
0101 #define M4U_PORT_CAM_BPCI       MTK_M4U_ID(M4U_LARB6_ID, 7)
0102 #define M4U_PORT_CAM_LCSO       MTK_M4U_ID(M4U_LARB6_ID, 8)
0103 #define M4U_PORT_CAM_CAM_RSSO_A     MTK_M4U_ID(M4U_LARB6_ID, 9)
0104 #define M4U_PORT_CAM_UFEO       MTK_M4U_ID(M4U_LARB6_ID, 10)
0105 #define M4U_PORT_CAM_SOCO       MTK_M4U_ID(M4U_LARB6_ID, 11)
0106 #define M4U_PORT_CAM_SOC1       MTK_M4U_ID(M4U_LARB6_ID, 12)
0107 #define M4U_PORT_CAM_SOC2       MTK_M4U_ID(M4U_LARB6_ID, 13)
0108 #define M4U_PORT_CAM_CCUI       MTK_M4U_ID(M4U_LARB6_ID, 14)
0109 #define M4U_PORT_CAM_CCUO       MTK_M4U_ID(M4U_LARB6_ID, 15)
0110 #define M4U_PORT_CAM_RAWI_A     MTK_M4U_ID(M4U_LARB6_ID, 16)
0111 #define M4U_PORT_CAM_CCUG       MTK_M4U_ID(M4U_LARB6_ID, 17)
0112 #define M4U_PORT_CAM_PSO        MTK_M4U_ID(M4U_LARB6_ID, 18)
0113 #define M4U_PORT_CAM_AFO_1      MTK_M4U_ID(M4U_LARB6_ID, 19)
0114 #define M4U_PORT_CAM_LSCI_2     MTK_M4U_ID(M4U_LARB6_ID, 20)
0115 #define M4U_PORT_CAM_PDI        MTK_M4U_ID(M4U_LARB6_ID, 21)
0116 #define M4U_PORT_CAM_FLKO       MTK_M4U_ID(M4U_LARB6_ID, 22)
0117 #define M4U_PORT_CAM_LMVO       MTK_M4U_ID(M4U_LARB6_ID, 23)
0118 #define M4U_PORT_CAM_UFGO       MTK_M4U_ID(M4U_LARB6_ID, 24)
0119 #define M4U_PORT_CAM_SPARE      MTK_M4U_ID(M4U_LARB6_ID, 25)
0120 #define M4U_PORT_CAM_SPARE_2        MTK_M4U_ID(M4U_LARB6_ID, 26)
0121 #define M4U_PORT_CAM_SPARE_3        MTK_M4U_ID(M4U_LARB6_ID, 27)
0122 #define M4U_PORT_CAM_SPARE_4        MTK_M4U_ID(M4U_LARB6_ID, 28)
0123 #define M4U_PORT_CAM_SPARE_5        MTK_M4U_ID(M4U_LARB6_ID, 29)
0124 #define M4U_PORT_CAM_SPARE_6        MTK_M4U_ID(M4U_LARB6_ID, 30)
0125
0126 /* CCU */
0127 #define M4U_PORT_CCU0           MTK_M4U_ID(M4U_LARB7_ID, 0)
0128 #define M4U_PORT_CCU1           MTK_M4U_ID(M4U_LARB7_ID, 1)
0129
0130 #endif