dt-bindings/memory/mt8173-larb-port.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2015-2016 MediaTek Inc.
0004  * Author: Yong Wu <yong.wu@mediatek.com>
0005  */
0006 #ifndef _DT_BINDINGS_MEMORY_MT8173_LARB_PORT_H_
0007 #define _DT_BINDINGS_MEMORY_MT8173_LARB_PORT_H_
0008
0009 #include <dt-bindings/memory/mtk-memory-port.h>
0010
0011 #define M4U_LARB0_ID            0
0012 #define M4U_LARB1_ID            1
0013 #define M4U_LARB2_ID            2
0014 #define M4U_LARB3_ID            3
0015 #define M4U_LARB4_ID            4
0016 #define M4U_LARB5_ID            5
0017
0018 /* larb0 */
0019 #define M4U_PORT_DISP_OVL0      MTK_M4U_ID(M4U_LARB0_ID, 0)
0020 #define M4U_PORT_DISP_RDMA0     MTK_M4U_ID(M4U_LARB0_ID, 1)
0021 #define M4U_PORT_DISP_WDMA0     MTK_M4U_ID(M4U_LARB0_ID, 2)
0022 #define M4U_PORT_DISP_OD_R      MTK_M4U_ID(M4U_LARB0_ID, 3)
0023 #define M4U_PORT_DISP_OD_W      MTK_M4U_ID(M4U_LARB0_ID, 4)
0024 #define M4U_PORT_MDP_RDMA0      MTK_M4U_ID(M4U_LARB0_ID, 5)
0025 #define M4U_PORT_MDP_WDMA       MTK_M4U_ID(M4U_LARB0_ID, 6)
0026 #define M4U_PORT_MDP_WROT0      MTK_M4U_ID(M4U_LARB0_ID, 7)
0027
0028 /* larb1 */
0029 #define M4U_PORT_HW_VDEC_MC_EXT     MTK_M4U_ID(M4U_LARB1_ID, 0)
0030 #define M4U_PORT_HW_VDEC_PP_EXT     MTK_M4U_ID(M4U_LARB1_ID, 1)
0031 #define M4U_PORT_HW_VDEC_UFO_EXT    MTK_M4U_ID(M4U_LARB1_ID, 2)
0032 #define M4U_PORT_HW_VDEC_VLD_EXT    MTK_M4U_ID(M4U_LARB1_ID, 3)
0033 #define M4U_PORT_HW_VDEC_VLD2_EXT   MTK_M4U_ID(M4U_LARB1_ID, 4)
0034 #define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB1_ID, 5)
0035 #define M4U_PORT_HW_VDEC_PRED_RD_EXT    MTK_M4U_ID(M4U_LARB1_ID, 6)
0036 #define M4U_PORT_HW_VDEC_PRED_WR_EXT    MTK_M4U_ID(M4U_LARB1_ID, 7)
0037 #define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB1_ID, 8)
0038 #define M4U_PORT_HW_VDEC_TILE       MTK_M4U_ID(M4U_LARB1_ID, 9)
0039
0040 /* larb2 */
0041 #define M4U_PORT_IMGO           MTK_M4U_ID(M4U_LARB2_ID, 0)
0042 #define M4U_PORT_RRZO           MTK_M4U_ID(M4U_LARB2_ID, 1)
0043 #define M4U_PORT_AAO            MTK_M4U_ID(M4U_LARB2_ID, 2)
0044 #define M4U_PORT_LCSO           MTK_M4U_ID(M4U_LARB2_ID, 3)
0045 #define M4U_PORT_ESFKO          MTK_M4U_ID(M4U_LARB2_ID, 4)
0046 #define M4U_PORT_IMGO_D         MTK_M4U_ID(M4U_LARB2_ID, 5)
0047 #define M4U_PORT_LSCI           MTK_M4U_ID(M4U_LARB2_ID, 6)
0048 #define M4U_PORT_LSCI_D         MTK_M4U_ID(M4U_LARB2_ID, 7)
0049 #define M4U_PORT_BPCI           MTK_M4U_ID(M4U_LARB2_ID, 8)
0050 #define M4U_PORT_BPCI_D         MTK_M4U_ID(M4U_LARB2_ID, 9)
0051 #define M4U_PORT_UFDI           MTK_M4U_ID(M4U_LARB2_ID, 10)
0052 #define M4U_PORT_IMGI           MTK_M4U_ID(M4U_LARB2_ID, 11)
0053 #define M4U_PORT_IMG2O          MTK_M4U_ID(M4U_LARB2_ID, 12)
0054 #define M4U_PORT_IMG3O          MTK_M4U_ID(M4U_LARB2_ID, 13)
0055 #define M4U_PORT_VIPI           MTK_M4U_ID(M4U_LARB2_ID, 14)
0056 #define M4U_PORT_VIP2I          MTK_M4U_ID(M4U_LARB2_ID, 15)
0057 #define M4U_PORT_VIP3I          MTK_M4U_ID(M4U_LARB2_ID, 16)
0058 #define M4U_PORT_LCEI           MTK_M4U_ID(M4U_LARB2_ID, 17)
0059 #define M4U_PORT_RB         MTK_M4U_ID(M4U_LARB2_ID, 18)
0060 #define M4U_PORT_RP         MTK_M4U_ID(M4U_LARB2_ID, 19)
0061 #define M4U_PORT_WR         MTK_M4U_ID(M4U_LARB2_ID, 20)
0062
0063 /* larb3 */
0064 #define M4U_PORT_VENC_RCPU      MTK_M4U_ID(M4U_LARB3_ID, 0)
0065 #define M4U_PORT_VENC_REC       MTK_M4U_ID(M4U_LARB3_ID, 1)
0066 #define M4U_PORT_VENC_BSDMA     MTK_M4U_ID(M4U_LARB3_ID, 2)
0067 #define M4U_PORT_VENC_SV_COMV       MTK_M4U_ID(M4U_LARB3_ID, 3)
0068 #define M4U_PORT_VENC_RD_COMV       MTK_M4U_ID(M4U_LARB3_ID, 4)
0069 #define M4U_PORT_JPGENC_RDMA        MTK_M4U_ID(M4U_LARB3_ID, 5)
0070 #define M4U_PORT_JPGENC_BSDMA       MTK_M4U_ID(M4U_LARB3_ID, 6)
0071 #define M4U_PORT_JPGDEC_WDMA        MTK_M4U_ID(M4U_LARB3_ID, 7)
0072 #define M4U_PORT_JPGDEC_BSDMA       MTK_M4U_ID(M4U_LARB3_ID, 8)
0073 #define M4U_PORT_VENC_CUR_LUMA      MTK_M4U_ID(M4U_LARB3_ID, 9)
0074 #define M4U_PORT_VENC_CUR_CHROMA    MTK_M4U_ID(M4U_LARB3_ID, 10)
0075 #define M4U_PORT_VENC_REF_LUMA      MTK_M4U_ID(M4U_LARB3_ID, 11)
0076 #define M4U_PORT_VENC_REF_CHROMA    MTK_M4U_ID(M4U_LARB3_ID, 12)
0077 #define M4U_PORT_VENC_NBM_RDMA      MTK_M4U_ID(M4U_LARB3_ID, 13)
0078 #define M4U_PORT_VENC_NBM_WDMA      MTK_M4U_ID(M4U_LARB3_ID, 14)
0079
0080 /* larb4 */
0081 #define M4U_PORT_DISP_OVL1      MTK_M4U_ID(M4U_LARB4_ID, 0)
0082 #define M4U_PORT_DISP_RDMA1     MTK_M4U_ID(M4U_LARB4_ID, 1)
0083 #define M4U_PORT_DISP_RDMA2     MTK_M4U_ID(M4U_LARB4_ID, 2)
0084 #define M4U_PORT_DISP_WDMA1     MTK_M4U_ID(M4U_LARB4_ID, 3)
0085 #define M4U_PORT_MDP_RDMA1      MTK_M4U_ID(M4U_LARB4_ID, 4)
0086 #define M4U_PORT_MDP_WROT1      MTK_M4U_ID(M4U_LARB4_ID, 5)
0087
0088 /* larb5 */
0089 #define M4U_PORT_VENC_RCPU_SET2     MTK_M4U_ID(M4U_LARB5_ID, 0)
0090 #define M4U_PORT_VENC_REC_FRM_SET2  MTK_M4U_ID(M4U_LARB5_ID, 1)
0091 #define M4U_PORT_VENC_REF_LUMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 2)
0092 #define M4U_PORT_VENC_REC_CHROMA_SET2   MTK_M4U_ID(M4U_LARB5_ID, 3)
0093 #define M4U_PORT_VENC_BSDMA_SET2    MTK_M4U_ID(M4U_LARB5_ID, 4)
0094 #define M4U_PORT_VENC_CUR_LUMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 5)
0095 #define M4U_PORT_VENC_CUR_CHROMA_SET2   MTK_M4U_ID(M4U_LARB5_ID, 6)
0096 #define M4U_PORT_VENC_RD_COMA_SET2  MTK_M4U_ID(M4U_LARB5_ID, 7)
0097 #define M4U_PORT_VENC_SV_COMA_SET2  MTK_M4U_ID(M4U_LARB5_ID, 8)
0098
0099 #endif