dt-bindings/memory/mt8167-larb-port.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2020 MediaTek Inc.
0004  * Copyright (c) 2020 BayLibre, SAS
0005  * Author: Honghui Zhang <honghui.zhang@mediatek.com>
0006  * Author: Fabien Parent <fparent@baylibre.com>
0007  */
0008 #ifndef _DT_BINDINGS_MEMORY_MT8167_LARB_PORT_H_
0009 #define _DT_BINDINGS_MEMORY_MT8167_LARB_PORT_H_
0010
0011 #include <dt-bindings/memory/mtk-memory-port.h>
0012
0013 #define M4U_LARB0_ID            0
0014 #define M4U_LARB1_ID            1
0015 #define M4U_LARB2_ID            2
0016
0017 /* larb0 */
0018 #define M4U_PORT_DISP_OVL0      MTK_M4U_ID(M4U_LARB0_ID, 0)
0019 #define M4U_PORT_DISP_RDMA0     MTK_M4U_ID(M4U_LARB0_ID, 1)
0020 #define M4U_PORT_DISP_WDMA0     MTK_M4U_ID(M4U_LARB0_ID, 2)
0021 #define M4U_PORT_DISP_RDMA1     MTK_M4U_ID(M4U_LARB0_ID, 3)
0022 #define M4U_PORT_MDP_RDMA       MTK_M4U_ID(M4U_LARB0_ID, 4)
0023 #define M4U_PORT_MDP_WDMA       MTK_M4U_ID(M4U_LARB0_ID, 5)
0024 #define M4U_PORT_MDP_WROT       MTK_M4U_ID(M4U_LARB0_ID, 6)
0025 #define M4U_PORT_DISP_FAKE      MTK_M4U_ID(M4U_LARB0_ID, 7)
0026
0027 /* larb1*/
0028 #define M4U_PORT_CAM_IMGO       MTK_M4U_ID(M4U_LARB1_ID, 0)
0029 #define M4U_PORT_CAM_IMG2O      MTK_M4U_ID(M4U_LARB1_ID, 1)
0030 #define M4U_PORT_CAM_LSCI       MTK_M4U_ID(M4U_LARB1_ID, 2)
0031 #define M4U_PORT_CAM_ESFKO      MTK_M4U_ID(M4U_LARB1_ID, 3)
0032 #define M4U_PORT_CAM_AAO        MTK_M4U_ID(M4U_LARB1_ID, 4)
0033 #define M4U_PORT_VENC_REC       MTK_M4U_ID(M4U_LARB1_ID, 5)
0034 #define M4U_PORT_VENC_BSDMA     MTK_M4U_ID(M4U_LARB1_ID, 6)
0035 #define M4U_PORT_VENC_RD_COMV       MTK_M4U_ID(M4U_LARB1_ID, 7)
0036 #define M4U_PORT_CAM_IMGI       MTK_M4U_ID(M4U_LARB1_ID, 8)
0037 #define M4U_PORT_VENC_CUR_LUMA      MTK_M4U_ID(M4U_LARB1_ID, 9)
0038 #define M4U_PORT_VENC_CUR_CHROMA    MTK_M4U_ID(M4U_LARB1_ID, 10)
0039 #define M4U_PORT_VENC_REF_LUMA      MTK_M4U_ID(M4U_LARB1_ID, 11)
0040 #define M4U_PORT_VENC_REF_CHROMA    MTK_M4U_ID(M4U_LARB1_ID, 12)
0041
0042 /* larb2*/
0043 #define M4U_PORT_HW_VDEC_MC_EXT     MTK_M4U_ID(M4U_LARB2_ID, 0)
0044 #define M4U_PORT_HW_VDEC_PP_EXT     MTK_M4U_ID(M4U_LARB2_ID, 1)
0045 #define M4U_PORT_HW_VDEC_VLD_EXT    MTK_M4U_ID(M4U_LARB2_ID, 2)
0046 #define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB2_ID, 3)
0047 #define M4U_PORT_HW_VDEC_PRED_RD_EXT    MTK_M4U_ID(M4U_LARB2_ID, 4)
0048 #define M4U_PORT_HW_VDEC_PRED_WR_EXT    MTK_M4U_ID(M4U_LARB2_ID, 5)
0049 #define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB2_ID, 6)
0050
0051 #endif