dt-bindings/memory/mt6779-larb-port.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2019 MediaTek Inc.
0004  * Author: Chao Hao <chao.hao@mediatek.com>
0005  */
0006
0007 #ifndef _DT_BINDINGS_MEMORY_MT6779_LARB_PORT_H_
0008 #define _DT_BINDINGS_MEMORY_MT6779_LARB_PORT_H_
0009
0010 #include <dt-bindings/memory/mtk-memory-port.h>
0011
0012 #define M4U_LARB0_ID             0
0013 #define M4U_LARB1_ID             1
0014 #define M4U_LARB2_ID             2
0015 #define M4U_LARB3_ID             3
0016 #define M4U_LARB4_ID             4
0017 #define M4U_LARB5_ID             5
0018 #define M4U_LARB6_ID             6
0019 #define M4U_LARB7_ID             7
0020 #define M4U_LARB8_ID             8
0021 #define M4U_LARB9_ID             9
0022 #define M4U_LARB10_ID            10
0023 #define M4U_LARB11_ID            11
0024
0025 /* larb0 */
0026 #define M4U_PORT_DISP_POSTMASK0      MTK_M4U_ID(M4U_LARB0_ID, 0)
0027 #define M4U_PORT_DISP_OVL0_HDR       MTK_M4U_ID(M4U_LARB0_ID, 1)
0028 #define M4U_PORT_DISP_OVL1_HDR       MTK_M4U_ID(M4U_LARB0_ID, 2)
0029 #define M4U_PORT_DISP_OVL0       MTK_M4U_ID(M4U_LARB0_ID, 3)
0030 #define M4U_PORT_DISP_OVL1       MTK_M4U_ID(M4U_LARB0_ID, 4)
0031 #define M4U_PORT_DISP_PVRIC0         MTK_M4U_ID(M4U_LARB0_ID, 5)
0032 #define M4U_PORT_DISP_RDMA0      MTK_M4U_ID(M4U_LARB0_ID, 6)
0033 #define M4U_PORT_DISP_WDMA0      MTK_M4U_ID(M4U_LARB0_ID, 7)
0034 #define M4U_PORT_DISP_FAKE0      MTK_M4U_ID(M4U_LARB0_ID, 8)
0035
0036 /* larb1 */
0037 #define M4U_PORT_DISP_OVL0_2L_HDR    MTK_M4U_ID(M4U_LARB1_ID, 0)
0038 #define M4U_PORT_DISP_OVL1_2L_HDR    MTK_M4U_ID(M4U_LARB1_ID, 1)
0039 #define M4U_PORT_DISP_OVL0_2L        MTK_M4U_ID(M4U_LARB1_ID, 2)
0040 #define M4U_PORT_DISP_OVL1_2L        MTK_M4U_ID(M4U_LARB1_ID, 3)
0041 #define M4U_PORT_DISP_RDMA1      MTK_M4U_ID(M4U_LARB1_ID, 4)
0042 #define M4U_PORT_MDP_PVRIC0      MTK_M4U_ID(M4U_LARB1_ID, 5)
0043 #define M4U_PORT_MDP_PVRIC1      MTK_M4U_ID(M4U_LARB1_ID, 6)
0044 #define M4U_PORT_MDP_RDMA0       MTK_M4U_ID(M4U_LARB1_ID, 7)
0045 #define M4U_PORT_MDP_RDMA1       MTK_M4U_ID(M4U_LARB1_ID, 8)
0046 #define M4U_PORT_MDP_WROT0_R         MTK_M4U_ID(M4U_LARB1_ID, 9)
0047 #define M4U_PORT_MDP_WROT0_W         MTK_M4U_ID(M4U_LARB1_ID, 10)
0048 #define M4U_PORT_MDP_WROT1_R         MTK_M4U_ID(M4U_LARB1_ID, 11)
0049 #define M4U_PORT_MDP_WROT1_W         MTK_M4U_ID(M4U_LARB1_ID, 12)
0050 #define M4U_PORT_DISP_FAKE1      MTK_M4U_ID(M4U_LARB1_ID, 13)
0051
0052 /* larb2-VDEC */
0053 #define M4U_PORT_HW_VDEC_MC_EXT          MTK_M4U_ID(M4U_LARB2_ID, 0)
0054 #define M4U_PORT_HW_VDEC_UFO_EXT         MTK_M4U_ID(M4U_LARB2_ID, 1)
0055 #define M4U_PORT_HW_VDEC_PP_EXT          MTK_M4U_ID(M4U_LARB2_ID, 2)
0056 #define M4U_PORT_HW_VDEC_PRED_RD_EXT     MTK_M4U_ID(M4U_LARB2_ID, 3)
0057 #define M4U_PORT_HW_VDEC_PRED_WR_EXT     MTK_M4U_ID(M4U_LARB2_ID, 4)
0058 #define M4U_PORT_HW_VDEC_PPWRAP_EXT      MTK_M4U_ID(M4U_LARB2_ID, 5)
0059 #define M4U_PORT_HW_VDEC_TILE_EXT        MTK_M4U_ID(M4U_LARB2_ID, 6)
0060 #define M4U_PORT_HW_VDEC_VLD_EXT         MTK_M4U_ID(M4U_LARB2_ID, 7)
0061 #define M4U_PORT_HW_VDEC_VLD2_EXT        MTK_M4U_ID(M4U_LARB2_ID, 8)
0062 #define M4U_PORT_HW_VDEC_AVC_MV_EXT      MTK_M4U_ID(M4U_LARB2_ID, 9)
0063 #define M4U_PORT_HW_VDEC_UFO_ENC_EXT     MTK_M4U_ID(M4U_LARB2_ID, 10)
0064 #define M4U_PORT_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(M4U_LARB2_ID, 11)
0065
0066 /* larb3-VENC */
0067 #define M4U_PORT_VENC_RCPU       MTK_M4U_ID(M4U_LARB3_ID, 0)
0068 #define M4U_PORT_VENC_REC        MTK_M4U_ID(M4U_LARB3_ID, 1)
0069 #define M4U_PORT_VENC_BSDMA      MTK_M4U_ID(M4U_LARB3_ID, 2)
0070 #define M4U_PORT_VENC_SV_COMV        MTK_M4U_ID(M4U_LARB3_ID, 3)
0071 #define M4U_PORT_VENC_RD_COMV        MTK_M4U_ID(M4U_LARB3_ID, 4)
0072 #define M4U_PORT_VENC_NBM_RDMA       MTK_M4U_ID(M4U_LARB3_ID, 5)
0073 #define M4U_PORT_VENC_NBM_RDMA_LITE  MTK_M4U_ID(M4U_LARB3_ID, 6)
0074 #define M4U_PORT_JPGENC_Y_RDMA       MTK_M4U_ID(M4U_LARB3_ID, 7)
0075 #define M4U_PORT_JPGENC_C_RDMA       MTK_M4U_ID(M4U_LARB3_ID, 8)
0076 #define M4U_PORT_JPGENC_Q_TABLE      MTK_M4U_ID(M4U_LARB3_ID, 9)
0077 #define M4U_PORT_JPGENC_BSDMA        MTK_M4U_ID(M4U_LARB3_ID, 10)
0078 #define M4U_PORT_JPGDEC_WDMA         MTK_M4U_ID(M4U_LARB3_ID, 11)
0079 #define M4U_PORT_JPGDEC_BSDMA        MTK_M4U_ID(M4U_LARB3_ID, 12)
0080 #define M4U_PORT_VENC_NBM_WDMA       MTK_M4U_ID(M4U_LARB3_ID, 13)
0081 #define M4U_PORT_VENC_NBM_WDMA_LITE  MTK_M4U_ID(M4U_LARB3_ID, 14)
0082 #define M4U_PORT_VENC_CUR_LUMA       MTK_M4U_ID(M4U_LARB3_ID, 15)
0083 #define M4U_PORT_VENC_CUR_CHROMA     MTK_M4U_ID(M4U_LARB3_ID, 16)
0084 #define M4U_PORT_VENC_REF_LUMA       MTK_M4U_ID(M4U_LARB3_ID, 17)
0085 #define M4U_PORT_VENC_REF_CHROMA     MTK_M4U_ID(M4U_LARB3_ID, 18)
0086
0087 /* larb4-dummy */
0088
0089 /* larb5-IMG */
0090 #define M4U_PORT_IMGI_D1         MTK_M4U_ID(M4U_LARB5_ID, 0)
0091 #define M4U_PORT_IMGBI_D1        MTK_M4U_ID(M4U_LARB5_ID, 1)
0092 #define M4U_PORT_DMGI_D1         MTK_M4U_ID(M4U_LARB5_ID, 2)
0093 #define M4U_PORT_DEPI_D1         MTK_M4U_ID(M4U_LARB5_ID, 3)
0094 #define M4U_PORT_LCEI_D1         MTK_M4U_ID(M4U_LARB5_ID, 4)
0095 #define M4U_PORT_SMTI_D1         MTK_M4U_ID(M4U_LARB5_ID, 5)
0096 #define M4U_PORT_SMTO_D2         MTK_M4U_ID(M4U_LARB5_ID, 6)
0097 #define M4U_PORT_SMTO_D1         MTK_M4U_ID(M4U_LARB5_ID, 7)
0098 #define M4U_PORT_CRZO_D1         MTK_M4U_ID(M4U_LARB5_ID, 8)
0099 #define M4U_PORT_IMG3O_D1        MTK_M4U_ID(M4U_LARB5_ID, 9)
0100 #define M4U_PORT_VIPI_D1         MTK_M4U_ID(M4U_LARB5_ID, 10)
0101 #define M4U_PORT_WPE_RDMA1       MTK_M4U_ID(M4U_LARB5_ID, 11)
0102 #define M4U_PORT_WPE_RDMA0       MTK_M4U_ID(M4U_LARB5_ID, 12)
0103 #define M4U_PORT_WPE_WDMA        MTK_M4U_ID(M4U_LARB5_ID, 13)
0104 #define M4U_PORT_TIMGO_D1        MTK_M4U_ID(M4U_LARB5_ID, 14)
0105 #define M4U_PORT_MFB_RDMA0       MTK_M4U_ID(M4U_LARB5_ID, 15)
0106 #define M4U_PORT_MFB_RDMA1       MTK_M4U_ID(M4U_LARB5_ID, 16)
0107 #define M4U_PORT_MFB_RDMA2       MTK_M4U_ID(M4U_LARB5_ID, 17)
0108 #define M4U_PORT_MFB_RDMA3       MTK_M4U_ID(M4U_LARB5_ID, 18)
0109 #define M4U_PORT_MFB_WDMA        MTK_M4U_ID(M4U_LARB5_ID, 19)
0110 #define M4U_PORT_RESERVE1        MTK_M4U_ID(M4U_LARB5_ID, 20)
0111 #define M4U_PORT_RESERVE2        MTK_M4U_ID(M4U_LARB5_ID, 21)
0112 #define M4U_PORT_RESERVE3        MTK_M4U_ID(M4U_LARB5_ID, 22)
0113 #define M4U_PORT_RESERVE4        MTK_M4U_ID(M4U_LARB5_ID, 23)
0114 #define M4U_PORT_RESERVE5        MTK_M4U_ID(M4U_LARB5_ID, 24)
0115 #define M4U_PORT_RESERVE6        MTK_M4U_ID(M4U_LARB5_ID, 25)
0116
0117 /* larb6-IMG-VPU */
0118 #define M4U_PORT_IMG_IPUO        MTK_M4U_ID(M4U_LARB6_ID, 0)
0119 #define M4U_PORT_IMG_IPU3O       MTK_M4U_ID(M4U_LARB6_ID, 1)
0120 #define M4U_PORT_IMG_IPUI        MTK_M4U_ID(M4U_LARB6_ID, 2)
0121
0122 /* larb7-DVS */
0123 #define M4U_PORT_DVS_RDMA        MTK_M4U_ID(M4U_LARB7_ID, 0)
0124 #define M4U_PORT_DVS_WDMA        MTK_M4U_ID(M4U_LARB7_ID, 1)
0125 #define M4U_PORT_DVP_RDMA        MTK_M4U_ID(M4U_LARB7_ID, 2)
0126 #define M4U_PORT_DVP_WDMA        MTK_M4U_ID(M4U_LARB7_ID, 3)
0127
0128 /* larb8-IPESYS */
0129 #define M4U_PORT_FDVT_RDA        MTK_M4U_ID(M4U_LARB8_ID, 0)
0130 #define M4U_PORT_FDVT_RDB        MTK_M4U_ID(M4U_LARB8_ID, 1)
0131 #define M4U_PORT_FDVT_WRA        MTK_M4U_ID(M4U_LARB8_ID, 2)
0132 #define M4U_PORT_FDVT_WRB        MTK_M4U_ID(M4U_LARB8_ID, 3)
0133 #define M4U_PORT_FE_RD0          MTK_M4U_ID(M4U_LARB8_ID, 4)
0134 #define M4U_PORT_FE_RD1          MTK_M4U_ID(M4U_LARB8_ID, 5)
0135 #define M4U_PORT_FE_WR0          MTK_M4U_ID(M4U_LARB8_ID, 6)
0136 #define M4U_PORT_FE_WR1          MTK_M4U_ID(M4U_LARB8_ID, 7)
0137 #define M4U_PORT_RSC_RDMA0       MTK_M4U_ID(M4U_LARB8_ID, 8)
0138 #define M4U_PORT_RSC_WDMA        MTK_M4U_ID(M4U_LARB8_ID, 9)
0139
0140 /* larb9-CAM */
0141 #define M4U_PORT_CAM_IMGO_R1_C       MTK_M4U_ID(M4U_LARB9_ID, 0)
0142 #define M4U_PORT_CAM_RRZO_R1_C       MTK_M4U_ID(M4U_LARB9_ID, 1)
0143 #define M4U_PORT_CAM_LSCI_R1_C       MTK_M4U_ID(M4U_LARB9_ID, 2)
0144 #define M4U_PORT_CAM_BPCI_R1_C       MTK_M4U_ID(M4U_LARB9_ID, 3)
0145 #define M4U_PORT_CAM_YUVO_R1_C       MTK_M4U_ID(M4U_LARB9_ID, 4)
0146 #define M4U_PORT_CAM_UFDI_R2_C       MTK_M4U_ID(M4U_LARB9_ID, 5)
0147 #define M4U_PORT_CAM_RAWI_R2_C       MTK_M4U_ID(M4U_LARB9_ID, 6)
0148 #define M4U_PORT_CAM_RAWI_R5_C       MTK_M4U_ID(M4U_LARB9_ID, 7)
0149 #define M4U_PORT_CAM_CAMSV_1         MTK_M4U_ID(M4U_LARB9_ID, 8)
0150 #define M4U_PORT_CAM_CAMSV_2         MTK_M4U_ID(M4U_LARB9_ID, 9)
0151 #define M4U_PORT_CAM_CAMSV_3         MTK_M4U_ID(M4U_LARB9_ID, 10)
0152 #define M4U_PORT_CAM_CAMSV_4         MTK_M4U_ID(M4U_LARB9_ID, 11)
0153 #define M4U_PORT_CAM_CAMSV_5         MTK_M4U_ID(M4U_LARB9_ID, 12)
0154 #define M4U_PORT_CAM_CAMSV_6         MTK_M4U_ID(M4U_LARB9_ID, 13)
0155 #define M4U_PORT_CAM_AAO_R1_C        MTK_M4U_ID(M4U_LARB9_ID, 14)
0156 #define M4U_PORT_CAM_AFO_R1_C        MTK_M4U_ID(M4U_LARB9_ID, 15)
0157 #define M4U_PORT_CAM_FLKO_R1_C       MTK_M4U_ID(M4U_LARB9_ID, 16)
0158 #define M4U_PORT_CAM_LCESO_R1_C      MTK_M4U_ID(M4U_LARB9_ID, 17)
0159 #define M4U_PORT_CAM_CRZO_R1_C       MTK_M4U_ID(M4U_LARB9_ID, 18)
0160 #define M4U_PORT_CAM_LTMSO_R1_C      MTK_M4U_ID(M4U_LARB9_ID, 19)
0161 #define M4U_PORT_CAM_RSSO_R1_C       MTK_M4U_ID(M4U_LARB9_ID, 20)
0162 #define M4U_PORT_CAM_CCUI        MTK_M4U_ID(M4U_LARB9_ID, 21)
0163 #define M4U_PORT_CAM_CCUO        MTK_M4U_ID(M4U_LARB9_ID, 22)
0164 #define M4U_PORT_CAM_FAKE        MTK_M4U_ID(M4U_LARB9_ID, 23)
0165
0166 /* larb10-CAM_A */
0167 #define M4U_PORT_CAM_IMGO_R1_A       MTK_M4U_ID(M4U_LARB10_ID, 0)
0168 #define M4U_PORT_CAM_RRZO_R1_A       MTK_M4U_ID(M4U_LARB10_ID, 1)
0169 #define M4U_PORT_CAM_LSCI_R1_A       MTK_M4U_ID(M4U_LARB10_ID, 2)
0170 #define M4U_PORT_CAM_BPCI_R1_A       MTK_M4U_ID(M4U_LARB10_ID, 3)
0171 #define M4U_PORT_CAM_YUVO_R1_A       MTK_M4U_ID(M4U_LARB10_ID, 4)
0172 #define M4U_PORT_CAM_UFDI_R2_A       MTK_M4U_ID(M4U_LARB10_ID, 5)
0173 #define M4U_PORT_CAM_RAWI_R2_A       MTK_M4U_ID(M4U_LARB10_ID, 6)
0174 #define M4U_PORT_CAM_RAWI_R5_A       MTK_M4U_ID(M4U_LARB10_ID, 7)
0175 #define M4U_PORT_CAM_IMGO_R1_B       MTK_M4U_ID(M4U_LARB10_ID, 8)
0176 #define M4U_PORT_CAM_RRZO_R1_B       MTK_M4U_ID(M4U_LARB10_ID, 9)
0177 #define M4U_PORT_CAM_LSCI_R1_B       MTK_M4U_ID(M4U_LARB10_ID, 10)
0178 #define M4U_PORT_CAM_BPCI_R1_B       MTK_M4U_ID(M4U_LARB10_ID, 11)
0179 #define M4U_PORT_CAM_YUVO_R1_B       MTK_M4U_ID(M4U_LARB10_ID, 12)
0180 #define M4U_PORT_CAM_UFDI_R2_B       MTK_M4U_ID(M4U_LARB10_ID, 13)
0181 #define M4U_PORT_CAM_RAWI_R2_B       MTK_M4U_ID(M4U_LARB10_ID, 14)
0182 #define M4U_PORT_CAM_RAWI_R5_B       MTK_M4U_ID(M4U_LARB10_ID, 15)
0183 #define M4U_PORT_CAM_CAMSV_0         MTK_M4U_ID(M4U_LARB10_ID, 16)
0184 #define M4U_PORT_CAM_AAO_R1_A        MTK_M4U_ID(M4U_LARB10_ID, 17)
0185 #define M4U_PORT_CAM_AFO_R1_A        MTK_M4U_ID(M4U_LARB10_ID, 18)
0186 #define M4U_PORT_CAM_FLKO_R1_A       MTK_M4U_ID(M4U_LARB10_ID, 19)
0187 #define M4U_PORT_CAM_LCESO_R1_A      MTK_M4U_ID(M4U_LARB10_ID, 20)
0188 #define M4U_PORT_CAM_CRZO_R1_A       MTK_M4U_ID(M4U_LARB10_ID, 21)
0189 #define M4U_PORT_CAM_AAO_R1_B        MTK_M4U_ID(M4U_LARB10_ID, 22)
0190 #define M4U_PORT_CAM_AFO_R1_B        MTK_M4U_ID(M4U_LARB10_ID, 23)
0191 #define M4U_PORT_CAM_FLKO_R1_B       MTK_M4U_ID(M4U_LARB10_ID, 24)
0192 #define M4U_PORT_CAM_LCESO_R1_B      MTK_M4U_ID(M4U_LARB10_ID, 25)
0193 #define M4U_PORT_CAM_CRZO_R1_B       MTK_M4U_ID(M4U_LARB10_ID, 26)
0194 #define M4U_PORT_CAM_LTMSO_R1_A      MTK_M4U_ID(M4U_LARB10_ID, 27)
0195 #define M4U_PORT_CAM_RSSO_R1_A       MTK_M4U_ID(M4U_LARB10_ID, 28)
0196 #define M4U_PORT_CAM_LTMSO_R1_B      MTK_M4U_ID(M4U_LARB10_ID, 29)
0197 #define M4U_PORT_CAM_RSSO_R1_B       MTK_M4U_ID(M4U_LARB10_ID, 30)
0198
0199 /* larb11-CAM-VPU */
0200 #define M4U_PORT_CAM_IPUO        MTK_M4U_ID(M4U_LARB11_ID, 0)
0201 #define M4U_PORT_CAM_IPU2O       MTK_M4U_ID(M4U_LARB11_ID, 1)
0202 #define M4U_PORT_CAM_IPU3O       MTK_M4U_ID(M4U_LARB11_ID, 2)
0203 #define M4U_PORT_CAM_IPUI        MTK_M4U_ID(M4U_LARB11_ID, 3)
0204 #define M4U_PORT_CAM_IPU2I       MTK_M4U_ID(M4U_LARB11_ID, 4)
0205
0206 #endif