dt-bindings/memory/mt2712-larb-port.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2017 MediaTek Inc.
0004  * Author: Yong Wu <yong.wu@mediatek.com>
0005  */
0006 #ifndef _DT_BINDINGS_MEMORY_MT2712_LARB_PORT_H_
0007 #define _DT_BINDINGS_MEMORY_MT2712_LARB_PORT_H_
0008
0009 #include <dt-bindings/memory/mtk-memory-port.h>
0010
0011 #define M4U_LARB0_ID            0
0012 #define M4U_LARB1_ID            1
0013 #define M4U_LARB2_ID            2
0014 #define M4U_LARB3_ID            3
0015 #define M4U_LARB4_ID            4
0016 #define M4U_LARB5_ID            5
0017 #define M4U_LARB6_ID            6
0018 #define M4U_LARB7_ID            7
0019 #define M4U_LARB8_ID            8
0020 #define M4U_LARB9_ID            9
0021
0022 /* larb0 */
0023 #define M4U_PORT_DISP_OVL0      MTK_M4U_ID(M4U_LARB0_ID, 0)
0024 #define M4U_PORT_DISP_RDMA0     MTK_M4U_ID(M4U_LARB0_ID, 1)
0025 #define M4U_PORT_DISP_WDMA0     MTK_M4U_ID(M4U_LARB0_ID, 2)
0026 #define M4U_PORT_DISP_OD_R      MTK_M4U_ID(M4U_LARB0_ID, 3)
0027 #define M4U_PORT_DISP_OD_W      MTK_M4U_ID(M4U_LARB0_ID, 4)
0028 #define M4U_PORT_MDP_RDMA0      MTK_M4U_ID(M4U_LARB0_ID, 5)
0029 #define M4U_PORT_MDP_WDMA       MTK_M4U_ID(M4U_LARB0_ID, 6)
0030 #define M4U_PORT_DISP_RDMA2     MTK_M4U_ID(M4U_LARB0_ID, 7)
0031
0032 /* larb1 */
0033 #define M4U_PORT_HW_VDEC_MC_EXT     MTK_M4U_ID(M4U_LARB1_ID, 0)
0034 #define M4U_PORT_HW_VDEC_PP_EXT     MTK_M4U_ID(M4U_LARB1_ID, 1)
0035 #define M4U_PORT_HW_VDEC_UFO_EXT    MTK_M4U_ID(M4U_LARB1_ID, 2)
0036 #define M4U_PORT_HW_VDEC_VLD_EXT    MTK_M4U_ID(M4U_LARB1_ID, 3)
0037 #define M4U_PORT_HW_VDEC_VLD2_EXT   MTK_M4U_ID(M4U_LARB1_ID, 4)
0038 #define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB1_ID, 5)
0039 #define M4U_PORT_HW_VDEC_PRED_RD_EXT    MTK_M4U_ID(M4U_LARB1_ID, 6)
0040 #define M4U_PORT_HW_VDEC_PRED_WR_EXT    MTK_M4U_ID(M4U_LARB1_ID, 7)
0041 #define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB1_ID, 8)
0042 #define M4U_PORT_HW_VDEC_TILE       MTK_M4U_ID(M4U_LARB1_ID, 9)
0043 #define M4U_PORT_HW_IMG_RESZ_EXT    MTK_M4U_ID(M4U_LARB1_ID, 10)
0044
0045 /* larb2 */
0046 #define M4U_PORT_CAM_DMA0       MTK_M4U_ID(M4U_LARB2_ID, 0)
0047 #define M4U_PORT_CAM_DMA1       MTK_M4U_ID(M4U_LARB2_ID, 1)
0048 #define M4U_PORT_CAM_DMA2       MTK_M4U_ID(M4U_LARB2_ID, 2)
0049
0050 /* larb3 */
0051 #define M4U_PORT_VENC_RCPU      MTK_M4U_ID(M4U_LARB3_ID, 0)
0052 #define M4U_PORT_VENC_REC       MTK_M4U_ID(M4U_LARB3_ID, 1)
0053 #define M4U_PORT_VENC_BSDMA     MTK_M4U_ID(M4U_LARB3_ID, 2)
0054 #define M4U_PORT_VENC_SV_COMV       MTK_M4U_ID(M4U_LARB3_ID, 3)
0055 #define M4U_PORT_VENC_RD_COMV       MTK_M4U_ID(M4U_LARB3_ID, 4)
0056 #define M4U_PORT_VENC_CUR_CHROMA    MTK_M4U_ID(M4U_LARB3_ID, 5)
0057 #define M4U_PORT_VENC_REF_CHROMA    MTK_M4U_ID(M4U_LARB3_ID, 6)
0058 #define M4U_PORT_VENC_CUR_LUMA      MTK_M4U_ID(M4U_LARB3_ID, 7)
0059 #define M4U_PORT_VENC_REF_LUMA      MTK_M4U_ID(M4U_LARB3_ID, 8)
0060
0061 /* larb4 */
0062 #define M4U_PORT_DISP_OVL1      MTK_M4U_ID(M4U_LARB4_ID, 0)
0063 #define M4U_PORT_DISP_RDMA1     MTK_M4U_ID(M4U_LARB4_ID, 1)
0064 #define M4U_PORT_DISP_WDMA1     MTK_M4U_ID(M4U_LARB4_ID, 2)
0065 #define M4U_PORT_DISP_OD1_R     MTK_M4U_ID(M4U_LARB4_ID, 3)
0066 #define M4U_PORT_DISP_OD1_W     MTK_M4U_ID(M4U_LARB4_ID, 4)
0067 #define M4U_PORT_MDP_RDMA1      MTK_M4U_ID(M4U_LARB4_ID, 5)
0068 #define M4U_PORT_MDP_WROT1      MTK_M4U_ID(M4U_LARB4_ID, 6)
0069
0070 /* larb5 */
0071 #define M4U_PORT_DISP_OVL2      MTK_M4U_ID(M4U_LARB5_ID, 0)
0072 #define M4U_PORT_DISP_WDMA2     MTK_M4U_ID(M4U_LARB5_ID, 1)
0073 #define M4U_PORT_MDP_RDMA2      MTK_M4U_ID(M4U_LARB5_ID, 2)
0074 #define M4U_PORT_MDP_WROT0      MTK_M4U_ID(M4U_LARB5_ID, 3)
0075
0076 /* larb6 */
0077 #define M4U_PORT_JPGDEC_WDMA_0      MTK_M4U_ID(M4U_LARB6_ID, 0)
0078 #define M4U_PORT_JPGDEC_WDMA_1      MTK_M4U_ID(M4U_LARB6_ID, 1)
0079 #define M4U_PORT_JPGDEC_BSDMA_0     MTK_M4U_ID(M4U_LARB6_ID, 2)
0080 #define M4U_PORT_JPGDEC_BSDMA_1     MTK_M4U_ID(M4U_LARB6_ID, 3)
0081
0082 /* larb7 */
0083 #define M4U_PORT_MDP_RDMA3      MTK_M4U_ID(M4U_LARB7_ID, 0)
0084 #define M4U_PORT_MDP_WROT2      MTK_M4U_ID(M4U_LARB7_ID, 1)
0085
0086 /* larb8 */
0087 #define M4U_PORT_VDO            MTK_M4U_ID(M4U_LARB8_ID, 0)
0088 #define M4U_PORT_NR         MTK_M4U_ID(M4U_LARB8_ID, 1)
0089 #define M4U_PORT_WR_CHANNEL0        MTK_M4U_ID(M4U_LARB8_ID, 2)
0090
0091 /* larb9 */
0092 #define M4U_PORT_TVD            MTK_M4U_ID(M4U_LARB9_ID, 0)
0093 #define M4U_PORT_WR_CHANNEL1        MTK_M4U_ID(M4U_LARB9_ID, 1)
0094
0095 #endif