dt-bindings/gce/mt8173-gce.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2018 MediaTek Inc.
0004  * Author: Houlong Wei <houlong.wei@mediatek.com>
0005  *
0006  */
0007
0008 #ifndef _DT_BINDINGS_GCE_MT8173_H
0009 #define _DT_BINDINGS_GCE_MT8173_H
0010
0011 /* GCE HW thread priority */
0012 #define CMDQ_THR_PRIO_LOWEST    0
0013 #define CMDQ_THR_PRIO_HIGHEST   1
0014
0015 /* GCE SUBSYS */
0016 #define SUBSYS_1400XXXX     1
0017 #define SUBSYS_1401XXXX     2
0018 #define SUBSYS_1402XXXX     3
0019
0020 /* GCE HW EVENT */
0021 #define CMDQ_EVENT_DISP_OVL0_SOF        11
0022 #define CMDQ_EVENT_DISP_OVL1_SOF        12
0023 #define CMDQ_EVENT_DISP_RDMA0_SOF       13
0024 #define CMDQ_EVENT_DISP_RDMA1_SOF       14
0025 #define CMDQ_EVENT_DISP_RDMA2_SOF       15
0026 #define CMDQ_EVENT_DISP_WDMA0_SOF       16
0027 #define CMDQ_EVENT_DISP_WDMA1_SOF       17
0028 #define CMDQ_EVENT_DISP_OVL0_EOF        39
0029 #define CMDQ_EVENT_DISP_OVL1_EOF        40
0030 #define CMDQ_EVENT_DISP_RDMA0_EOF       41
0031 #define CMDQ_EVENT_DISP_RDMA1_EOF       42
0032 #define CMDQ_EVENT_DISP_RDMA2_EOF       43
0033 #define CMDQ_EVENT_DISP_WDMA0_EOF       44
0034 #define CMDQ_EVENT_DISP_WDMA1_EOF       45
0035 #define CMDQ_EVENT_MUTEX0_STREAM_EOF        53
0036 #define CMDQ_EVENT_MUTEX1_STREAM_EOF        54
0037 #define CMDQ_EVENT_MUTEX2_STREAM_EOF        55
0038 #define CMDQ_EVENT_MUTEX3_STREAM_EOF        56
0039 #define CMDQ_EVENT_MUTEX4_STREAM_EOF        57
0040 #define CMDQ_EVENT_DISP_RDMA0_UNDERRUN      63
0041 #define CMDQ_EVENT_DISP_RDMA1_UNDERRUN      64
0042 #define CMDQ_EVENT_DISP_RDMA2_UNDERRUN      65
0043
0044 #endif