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0001 #ifndef __DT_BINDINGS_DMA_JZ4780_DMA_H__
0002 #define __DT_BINDINGS_DMA_JZ4780_DMA_H__
0003 
0004 /*
0005  * Request type numbers for the JZ4780 DMA controller (written to the DRTn
0006  * register for the channel).
0007  */
0008 #define JZ4780_DMA_I2S1_TX  0x4
0009 #define JZ4780_DMA_I2S1_RX  0x5
0010 #define JZ4780_DMA_I2S0_TX  0x6
0011 #define JZ4780_DMA_I2S0_RX  0x7
0012 #define JZ4780_DMA_AUTO     0x8
0013 #define JZ4780_DMA_SADC_RX  0x9
0014 #define JZ4780_DMA_UART4_TX 0xc
0015 #define JZ4780_DMA_UART4_RX 0xd
0016 #define JZ4780_DMA_UART3_TX 0xe
0017 #define JZ4780_DMA_UART3_RX 0xf
0018 #define JZ4780_DMA_UART2_TX 0x10
0019 #define JZ4780_DMA_UART2_RX 0x11
0020 #define JZ4780_DMA_UART1_TX 0x12
0021 #define JZ4780_DMA_UART1_RX 0x13
0022 #define JZ4780_DMA_UART0_TX 0x14
0023 #define JZ4780_DMA_UART0_RX 0x15
0024 #define JZ4780_DMA_SSI0_TX  0x16
0025 #define JZ4780_DMA_SSI0_RX  0x17
0026 #define JZ4780_DMA_SSI1_TX  0x18
0027 #define JZ4780_DMA_SSI1_RX  0x19
0028 #define JZ4780_DMA_MSC0_TX  0x1a
0029 #define JZ4780_DMA_MSC0_RX  0x1b
0030 #define JZ4780_DMA_MSC1_TX  0x1c
0031 #define JZ4780_DMA_MSC1_RX  0x1d
0032 #define JZ4780_DMA_MSC2_TX  0x1e
0033 #define JZ4780_DMA_MSC2_RX  0x1f
0034 #define JZ4780_DMA_PCM0_TX  0x20
0035 #define JZ4780_DMA_PCM0_RX  0x21
0036 #define JZ4780_DMA_SMB0_TX  0x24
0037 #define JZ4780_DMA_SMB0_RX  0x25
0038 #define JZ4780_DMA_SMB1_TX  0x26
0039 #define JZ4780_DMA_SMB1_RX  0x27
0040 #define JZ4780_DMA_SMB2_TX  0x28
0041 #define JZ4780_DMA_SMB2_RX  0x29
0042 #define JZ4780_DMA_SMB3_TX  0x2a
0043 #define JZ4780_DMA_SMB3_RX  0x2b
0044 #define JZ4780_DMA_SMB4_TX  0x2c
0045 #define JZ4780_DMA_SMB4_RX  0x2d
0046 #define JZ4780_DMA_DES_TX   0x2e
0047 #define JZ4780_DMA_DES_RX   0x2f
0048 
0049 #endif /* __DT_BINDINGS_DMA_JZ4780_DMA_H__ */