dt-bindings/dma/jz4775-dma.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * This header provides macros for JZ4775 DMA bindings.
0004  *
0005  * Copyright (c) 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
0006  */
0007
0008 #ifndef __DT_BINDINGS_DMA_JZ4775_DMA_H__
0009 #define __DT_BINDINGS_DMA_JZ4775_DMA_H__
0010
0011 /*
0012  * Request type numbers for the JZ4775 DMA controller (written to the DRTn
0013  * register for the channel).
0014  */
0015 #define JZ4775_DMA_I2S0_TX  0x6
0016 #define JZ4775_DMA_I2S0_RX  0x7
0017 #define JZ4775_DMA_AUTO     0x8
0018 #define JZ4775_DMA_SADC_RX  0x9
0019 #define JZ4775_DMA_UART3_TX 0x0e
0020 #define JZ4775_DMA_UART3_RX 0x0f
0021 #define JZ4775_DMA_UART2_TX 0x10
0022 #define JZ4775_DMA_UART2_RX 0x11
0023 #define JZ4775_DMA_UART1_TX 0x12
0024 #define JZ4775_DMA_UART1_RX 0x13
0025 #define JZ4775_DMA_UART0_TX 0x14
0026 #define JZ4775_DMA_UART0_RX 0x15
0027 #define JZ4775_DMA_SSI0_TX  0x16
0028 #define JZ4775_DMA_SSI0_RX  0x17
0029 #define JZ4775_DMA_MSC0_TX  0x1a
0030 #define JZ4775_DMA_MSC0_RX  0x1b
0031 #define JZ4775_DMA_MSC1_TX  0x1c
0032 #define JZ4775_DMA_MSC1_RX  0x1d
0033 #define JZ4775_DMA_MSC2_TX  0x1e
0034 #define JZ4775_DMA_MSC2_RX  0x1f
0035 #define JZ4775_DMA_PCM0_TX  0x20
0036 #define JZ4775_DMA_PCM0_RX  0x21
0037 #define JZ4775_DMA_SMB0_TX  0x24
0038 #define JZ4775_DMA_SMB0_RX  0x25
0039 #define JZ4775_DMA_SMB1_TX  0x26
0040 #define JZ4775_DMA_SMB1_RX  0x27
0041 #define JZ4775_DMA_SMB2_TX  0x28
0042 #define JZ4775_DMA_SMB2_RX  0x29
0043
0044 #endif /* __DT_BINDINGS_DMA_JZ4775_DMA_H__ */