dt-bindings/clock/xlnx-zynqmp-clk.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Xilinx Zynq MPSoC Firmware layer
0004  *
0005  *  Copyright (C) 2014-2018 Xilinx, Inc.
0006  *
0007  */
0008
0009 #ifndef _DT_BINDINGS_CLK_ZYNQMP_H
0010 #define _DT_BINDINGS_CLK_ZYNQMP_H
0011
0012 #define IOPLL           0
0013 #define RPLL            1
0014 #define APLL            2
0015 #define DPLL            3
0016 #define VPLL            4
0017 #define IOPLL_TO_FPD        5
0018 #define RPLL_TO_FPD     6
0019 #define APLL_TO_LPD     7
0020 #define DPLL_TO_LPD     8
0021 #define VPLL_TO_LPD     9
0022 #define ACPU            10
0023 #define ACPU_HALF       11
0024 #define DBF_FPD         12
0025 #define DBF_LPD         13
0026 #define DBG_TRACE       14
0027 #define DBG_TSTMP       15
0028 #define DP_VIDEO_REF        16
0029 #define DP_AUDIO_REF        17
0030 #define DP_STC_REF      18
0031 #define GDMA_REF        19
0032 #define DPDMA_REF       20
0033 #define DDR_REF         21
0034 #define SATA_REF        22
0035 #define PCIE_REF        23
0036 #define GPU_REF         24
0037 #define GPU_PP0_REF     25
0038 #define GPU_PP1_REF     26
0039 #define TOPSW_MAIN      27
0040 #define TOPSW_LSBUS     28
0041 #define GTGREF0_REF     29
0042 #define LPD_SWITCH      30
0043 #define LPD_LSBUS       31
0044 #define USB0_BUS_REF        32
0045 #define USB1_BUS_REF        33
0046 #define USB3_DUAL_REF       34
0047 #define USB0            35
0048 #define USB1            36
0049 #define CPU_R5          37
0050 #define CPU_R5_CORE     38
0051 #define CSU_SPB         39
0052 #define CSU_PLL         40
0053 #define PCAP            41
0054 #define IOU_SWITCH      42
0055 #define GEM_TSU_REF     43
0056 #define GEM_TSU         44
0057 #define GEM0_TX         45
0058 #define GEM1_TX         46
0059 #define GEM2_TX         47
0060 #define GEM3_TX         48
0061 #define GEM0_RX         49
0062 #define GEM1_RX         50
0063 #define GEM2_RX         51
0064 #define GEM3_RX         52
0065 #define QSPI_REF        53
0066 #define SDIO0_REF       54
0067 #define SDIO1_REF       55
0068 #define UART0_REF       56
0069 #define UART1_REF       57
0070 #define SPI0_REF        58
0071 #define SPI1_REF        59
0072 #define NAND_REF        60
0073 #define I2C0_REF        61
0074 #define I2C1_REF        62
0075 #define CAN0_REF        63
0076 #define CAN1_REF        64
0077 #define CAN0            65
0078 #define CAN1            66
0079 #define DLL_REF         67
0080 #define ADMA_REF        68
0081 #define TIMESTAMP_REF       69
0082 #define AMS_REF         70
0083 #define PL0_REF         71
0084 #define PL1_REF         72
0085 #define PL2_REF         73
0086 #define PL3_REF         74
0087 #define WDT         75
0088 #define IOPLL_INT       76
0089 #define IOPLL_PRE_SRC       77
0090 #define IOPLL_HALF      78
0091 #define IOPLL_INT_MUX       79
0092 #define IOPLL_POST_SRC      80
0093 #define RPLL_INT        81
0094 #define RPLL_PRE_SRC        82
0095 #define RPLL_HALF       83
0096 #define RPLL_INT_MUX        84
0097 #define RPLL_POST_SRC       85
0098 #define APLL_INT        86
0099 #define APLL_PRE_SRC        87
0100 #define APLL_HALF       88
0101 #define APLL_INT_MUX        89
0102 #define APLL_POST_SRC       90
0103 #define DPLL_INT        91
0104 #define DPLL_PRE_SRC        92
0105 #define DPLL_HALF       93
0106 #define DPLL_INT_MUX        94
0107 #define DPLL_POST_SRC       95
0108 #define VPLL_INT        96
0109 #define VPLL_PRE_SRC        97
0110 #define VPLL_HALF       98
0111 #define VPLL_INT_MUX        99
0112 #define VPLL_POST_SRC       100
0113 #define CAN0_MIO        101
0114 #define CAN1_MIO        102
0115 #define ACPU_FULL       103
0116 #define GEM0_REF        104
0117 #define GEM1_REF        105
0118 #define GEM2_REF        106
0119 #define GEM3_REF        107
0120 #define GEM0_REF_UNG        108
0121 #define GEM1_REF_UNG        109
0122 #define GEM2_REF_UNG        110
0123 #define GEM3_REF_UNG        111
0124 #define LPD_WDT         112
0125
0126 #endif