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0001 /* SPDX-License-Identifier: GPL-2.0 */ 0002 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */ 0003 0004 #ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H 0005 #define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H 0006 0007 /** 0008 * @file 0009 * @defgroup bpmp_clock_ids Clock ID's 0010 * @{ 0011 */ 0012 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */ 0013 #define TEGRA234_CLK_AHUB 4U 0014 /** @brief output of gate CLK_ENB_APB2APE */ 0015 #define TEGRA234_CLK_APB2APE 5U 0016 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */ 0017 #define TEGRA234_CLK_APE 6U 0018 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */ 0019 #define TEGRA234_CLK_AUD_MCLK 7U 0020 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */ 0021 #define TEGRA234_CLK_DMIC1 15U 0022 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */ 0023 #define TEGRA234_CLK_DMIC2 16U 0024 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */ 0025 #define TEGRA234_CLK_DMIC3 17U 0026 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */ 0027 #define TEGRA234_CLK_DMIC4 18U 0028 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */ 0029 #define TEGRA234_CLK_DSPK1 29U 0030 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */ 0031 #define TEGRA234_CLK_DSPK2 30U 0032 /** 0033 * @brief controls the EMC clock frequency. 0034 * @details Doing a clk_set_rate on this clock will select the 0035 * appropriate clock source, program the source rate and execute a 0036 * specific sequence to switch to the new clock source for both memory 0037 * controllers. This can be used to control the balance between memory 0038 * throughput and memory controller power. 0039 */ 0040 #define TEGRA234_CLK_EMC 31U 0041 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */ 0042 #define TEGRA234_CLK_HOST1X 46U 0043 /** @brief output of gate CLK_ENB_FUSE */ 0044 #define TEGRA234_CLK_FUSE 40U 0045 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */ 0046 #define TEGRA234_CLK_I2C1 48U 0047 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */ 0048 #define TEGRA234_CLK_I2C2 49U 0049 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */ 0050 #define TEGRA234_CLK_I2C3 50U 0051 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */ 0052 #define TEGRA234_CLK_I2C4 51U 0053 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */ 0054 #define TEGRA234_CLK_I2C6 52U 0055 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */ 0056 #define TEGRA234_CLK_I2C7 53U 0057 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */ 0058 #define TEGRA234_CLK_I2C8 54U 0059 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */ 0060 #define TEGRA234_CLK_I2C9 55U 0061 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */ 0062 #define TEGRA234_CLK_I2S1 56U 0063 /** @brief clock recovered from I2S1 input */ 0064 #define TEGRA234_CLK_I2S1_SYNC_INPUT 57U 0065 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */ 0066 #define TEGRA234_CLK_I2S2 58U 0067 /** @brief clock recovered from I2S2 input */ 0068 #define TEGRA234_CLK_I2S2_SYNC_INPUT 59U 0069 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */ 0070 #define TEGRA234_CLK_I2S3 60U 0071 /** @brief clock recovered from I2S3 input */ 0072 #define TEGRA234_CLK_I2S3_SYNC_INPUT 61U 0073 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */ 0074 #define TEGRA234_CLK_I2S4 62U 0075 /** @brief clock recovered from I2S4 input */ 0076 #define TEGRA234_CLK_I2S4_SYNC_INPUT 63U 0077 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */ 0078 #define TEGRA234_CLK_I2S5 64U 0079 /** @brief clock recovered from I2S5 input */ 0080 #define TEGRA234_CLK_I2S5_SYNC_INPUT 65U 0081 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S6 */ 0082 #define TEGRA234_CLK_I2S6 66U 0083 /** @brief clock recovered from I2S6 input */ 0084 #define TEGRA234_CLK_I2S6_SYNC_INPUT 67U 0085 /** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */ 0086 #define TEGRA234_CLK_PLLA 93U 0087 /** @brief PLLP clk output */ 0088 #define TEGRA234_CLK_PLLP_OUT0 102U 0089 /** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */ 0090 #define TEGRA234_CLK_PLLA_OUT0 104U 0091 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */ 0092 #define TEGRA234_CLK_PWM1 105U 0093 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */ 0094 #define TEGRA234_CLK_PWM2 106U 0095 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */ 0096 #define TEGRA234_CLK_PWM3 107U 0097 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */ 0098 #define TEGRA234_CLK_PWM4 108U 0099 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */ 0100 #define TEGRA234_CLK_PWM5 109U 0101 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */ 0102 #define TEGRA234_CLK_PWM6 110U 0103 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */ 0104 #define TEGRA234_CLK_PWM7 111U 0105 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */ 0106 #define TEGRA234_CLK_PWM8 112U 0107 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ 0108 #define TEGRA234_CLK_SDMMC4 123U 0109 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */ 0110 #define TEGRA234_CLK_SYNC_DMIC1 139U 0111 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */ 0112 #define TEGRA234_CLK_SYNC_DMIC2 140U 0113 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */ 0114 #define TEGRA234_CLK_SYNC_DMIC3 141U 0115 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */ 0116 #define TEGRA234_CLK_SYNC_DMIC4 142U 0117 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */ 0118 #define TEGRA234_CLK_SYNC_DSPK1 143U 0119 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */ 0120 #define TEGRA234_CLK_SYNC_DSPK2 144U 0121 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */ 0122 #define TEGRA234_CLK_SYNC_I2S1 145U 0123 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */ 0124 #define TEGRA234_CLK_SYNC_I2S2 146U 0125 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */ 0126 #define TEGRA234_CLK_SYNC_I2S3 147U 0127 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */ 0128 #define TEGRA234_CLK_SYNC_I2S4 148U 0129 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */ 0130 #define TEGRA234_CLK_SYNC_I2S5 149U 0131 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */ 0132 #define TEGRA234_CLK_SYNC_I2S6 150U 0133 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ 0134 #define TEGRA234_CLK_UARTA 155U 0135 /** @brief output of gate CLK_ENB_PEX1_CORE_6 */ 0136 #define TEGRA234_CLK_PEX1_C6_CORE 161U 0137 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */ 0138 #define TEGRA234_CLK_VIC 167U 0139 /** @brief output of gate CLK_ENB_PEX2_CORE_7 */ 0140 #define TEGRA234_CLK_PEX2_C7_CORE 171U 0141 /** @brief output of gate CLK_ENB_PEX2_CORE_8 */ 0142 #define TEGRA234_CLK_PEX2_C8_CORE 172U 0143 /** @brief output of gate CLK_ENB_PEX2_CORE_9 */ 0144 #define TEGRA234_CLK_PEX2_C9_CORE 173U 0145 /** @brief output of gate CLK_ENB_PEX2_CORE_10 */ 0146 #define TEGRA234_CLK_PEX2_C10_CORE 187U 0147 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 switch divider output */ 0148 #define TEGRA234_CLK_QSPI0_2X_PM 192U 0149 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 switch divider output */ 0150 #define TEGRA234_CLK_QSPI1_2X_PM 193U 0151 /** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 */ 0152 #define TEGRA234_CLK_QSPI0_PM 194U 0153 /** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 */ 0154 #define TEGRA234_CLK_QSPI1_PM 195U 0155 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */ 0156 #define TEGRA234_CLK_SDMMC_LEGACY_TM 219U 0157 /** @brief output of gate CLK_ENB_PEX0_CORE_0 */ 0158 #define TEGRA234_CLK_PEX0_C0_CORE 220U 0159 /** @brief output of gate CLK_ENB_PEX0_CORE_1 */ 0160 #define TEGRA234_CLK_PEX0_C1_CORE 221U 0161 /** @brief output of gate CLK_ENB_PEX0_CORE_2 */ 0162 #define TEGRA234_CLK_PEX0_C2_CORE 222U 0163 /** @brief output of gate CLK_ENB_PEX0_CORE_3 */ 0164 #define TEGRA234_CLK_PEX0_C3_CORE 223U 0165 /** @brief output of gate CLK_ENB_PEX0_CORE_4 */ 0166 #define TEGRA234_CLK_PEX0_C4_CORE 224U 0167 /** @brief output of gate CLK_ENB_PEX1_CORE_5 */ 0168 #define TEGRA234_CLK_PEX1_C5_CORE 225U 0169 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */ 0170 #define TEGRA234_CLK_PLLC4 237U 0171 /** @brief RX clock recovered from MGBE0 lane input */ 0172 #define TEGRA234_CLK_MGBE0_RX_INPUT 248U 0173 /** @brief RX clock recovered from MGBE1 lane input */ 0174 #define TEGRA234_CLK_MGBE1_RX_INPUT 249U 0175 /** @brief RX clock recovered from MGBE2 lane input */ 0176 #define TEGRA234_CLK_MGBE2_RX_INPUT 250U 0177 /** @brief RX clock recovered from MGBE3 lane input */ 0178 #define TEGRA234_CLK_MGBE3_RX_INPUT 251U 0179 /** @brief 32K input clock provided by PMIC */ 0180 #define TEGRA234_CLK_CLK_32K 289U 0181 /** @brief Monitored branch of MBGE0 RX input clock */ 0182 #define TEGRA234_CLK_MGBE0_RX_INPUT_M 357U 0183 /** @brief Monitored branch of MBGE1 RX input clock */ 0184 #define TEGRA234_CLK_MGBE1_RX_INPUT_M 358U 0185 /** @brief Monitored branch of MBGE2 RX input clock */ 0186 #define TEGRA234_CLK_MGBE2_RX_INPUT_M 359U 0187 /** @brief Monitored branch of MBGE3 RX input clock */ 0188 #define TEGRA234_CLK_MGBE3_RX_INPUT_M 360U 0189 /** @brief Monitored branch of MGBE0 RX PCS mux output */ 0190 #define TEGRA234_CLK_MGBE0_RX_PCS_M 361U 0191 /** @brief Monitored branch of MGBE1 RX PCS mux output */ 0192 #define TEGRA234_CLK_MGBE1_RX_PCS_M 362U 0193 /** @brief Monitored branch of MGBE2 RX PCS mux output */ 0194 #define TEGRA234_CLK_MGBE2_RX_PCS_M 363U 0195 /** @brief Monitored branch of MGBE3 RX PCS mux output */ 0196 #define TEGRA234_CLK_MGBE3_RX_PCS_M 364U 0197 /** @brief RX PCS clock recovered from MGBE0 lane input */ 0198 #define TEGRA234_CLK_MGBE0_RX_PCS_INPUT 369U 0199 /** @brief RX PCS clock recovered from MGBE1 lane input */ 0200 #define TEGRA234_CLK_MGBE1_RX_PCS_INPUT 370U 0201 /** @brief RX PCS clock recovered from MGBE2 lane input */ 0202 #define TEGRA234_CLK_MGBE2_RX_PCS_INPUT 371U 0203 /** @brief RX PCS clock recovered from MGBE3 lane input */ 0204 #define TEGRA234_CLK_MGBE3_RX_PCS_INPUT 372U 0205 /** @brief output of mux controlled by GBE_UPHY_MGBE0_RX_PCS_CLK_SRC_SEL */ 0206 #define TEGRA234_CLK_MGBE0_RX_PCS 373U 0207 /** @brief GBE_UPHY_MGBE0_TX_CLK divider gated output */ 0208 #define TEGRA234_CLK_MGBE0_TX 374U 0209 /** @brief GBE_UPHY_MGBE0_TX_PCS_CLK divider gated output */ 0210 #define TEGRA234_CLK_MGBE0_TX_PCS 375U 0211 /** @brief GBE_UPHY_MGBE0_MAC_CLK divider output */ 0212 #define TEGRA234_CLK_MGBE0_MAC_DIVIDER 376U 0213 /** @brief GBE_UPHY_MGBE0_MAC_CLK gate output */ 0214 #define TEGRA234_CLK_MGBE0_MAC 377U 0215 /** @brief GBE_UPHY_MGBE0_MACSEC_CLK gate output */ 0216 #define TEGRA234_CLK_MGBE0_MACSEC 378U 0217 /** @brief GBE_UPHY_MGBE0_EEE_PCS_CLK gate output */ 0218 #define TEGRA234_CLK_MGBE0_EEE_PCS 379U 0219 /** @brief GBE_UPHY_MGBE0_APP_CLK gate output */ 0220 #define TEGRA234_CLK_MGBE0_APP 380U 0221 /** @brief GBE_UPHY_MGBE0_PTP_REF_CLK divider gated output */ 0222 #define TEGRA234_CLK_MGBE0_PTP_REF 381U 0223 /** @brief output of mux controlled by GBE_UPHY_MGBE1_RX_PCS_CLK_SRC_SEL */ 0224 #define TEGRA234_CLK_MGBE1_RX_PCS 382U 0225 /** @brief GBE_UPHY_MGBE1_TX_CLK divider gated output */ 0226 #define TEGRA234_CLK_MGBE1_TX 383U 0227 /** @brief GBE_UPHY_MGBE1_TX_PCS_CLK divider gated output */ 0228 #define TEGRA234_CLK_MGBE1_TX_PCS 384U 0229 /** @brief GBE_UPHY_MGBE1_MAC_CLK divider output */ 0230 #define TEGRA234_CLK_MGBE1_MAC_DIVIDER 385U 0231 /** @brief GBE_UPHY_MGBE1_MAC_CLK gate output */ 0232 #define TEGRA234_CLK_MGBE1_MAC 386U 0233 /** @brief GBE_UPHY_MGBE1_EEE_PCS_CLK gate output */ 0234 #define TEGRA234_CLK_MGBE1_EEE_PCS 388U 0235 /** @brief GBE_UPHY_MGBE1_APP_CLK gate output */ 0236 #define TEGRA234_CLK_MGBE1_APP 389U 0237 /** @brief GBE_UPHY_MGBE1_PTP_REF_CLK divider gated output */ 0238 #define TEGRA234_CLK_MGBE1_PTP_REF 390U 0239 /** @brief output of mux controlled by GBE_UPHY_MGBE2_RX_PCS_CLK_SRC_SEL */ 0240 #define TEGRA234_CLK_MGBE2_RX_PCS 391U 0241 /** @brief GBE_UPHY_MGBE2_TX_CLK divider gated output */ 0242 #define TEGRA234_CLK_MGBE2_TX 392U 0243 /** @brief GBE_UPHY_MGBE2_TX_PCS_CLK divider gated output */ 0244 #define TEGRA234_CLK_MGBE2_TX_PCS 393U 0245 /** @brief GBE_UPHY_MGBE2_MAC_CLK divider output */ 0246 #define TEGRA234_CLK_MGBE2_MAC_DIVIDER 394U 0247 /** @brief GBE_UPHY_MGBE2_MAC_CLK gate output */ 0248 #define TEGRA234_CLK_MGBE2_MAC 395U 0249 /** @brief GBE_UPHY_MGBE2_EEE_PCS_CLK gate output */ 0250 #define TEGRA234_CLK_MGBE2_EEE_PCS 397U 0251 /** @brief GBE_UPHY_MGBE2_APP_CLK gate output */ 0252 #define TEGRA234_CLK_MGBE2_APP 398U 0253 /** @brief GBE_UPHY_MGBE2_PTP_REF_CLK divider gated output */ 0254 #define TEGRA234_CLK_MGBE2_PTP_REF 399U 0255 /** @brief output of mux controlled by GBE_UPHY_MGBE3_RX_PCS_CLK_SRC_SEL */ 0256 #define TEGRA234_CLK_MGBE3_RX_PCS 400U 0257 /** @brief GBE_UPHY_MGBE3_TX_CLK divider gated output */ 0258 #define TEGRA234_CLK_MGBE3_TX 401U 0259 /** @brief GBE_UPHY_MGBE3_TX_PCS_CLK divider gated output */ 0260 #define TEGRA234_CLK_MGBE3_TX_PCS 402U 0261 /** @brief GBE_UPHY_MGBE3_MAC_CLK divider output */ 0262 #define TEGRA234_CLK_MGBE3_MAC_DIVIDER 403U 0263 /** @brief GBE_UPHY_MGBE3_MAC_CLK gate output */ 0264 #define TEGRA234_CLK_MGBE3_MAC 404U 0265 /** @brief GBE_UPHY_MGBE3_MACSEC_CLK gate output */ 0266 #define TEGRA234_CLK_MGBE3_MACSEC 405U 0267 /** @brief GBE_UPHY_MGBE3_EEE_PCS_CLK gate output */ 0268 #define TEGRA234_CLK_MGBE3_EEE_PCS 406U 0269 /** @brief GBE_UPHY_MGBE3_APP_CLK gate output */ 0270 #define TEGRA234_CLK_MGBE3_APP 407U 0271 /** @brief GBE_UPHY_MGBE3_PTP_REF_CLK divider gated output */ 0272 #define TEGRA234_CLK_MGBE3_PTP_REF 408U 0273 /** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */ 0274 #define TEGRA234_CLK_AZA_2XBIT 457U 0275 /** @brief aza_2xbitclk / 2 (aza_bitclk) */ 0276 #define TEGRA234_CLK_AZA_BIT 458U 0277 0278 #endif
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