dt-bindings/clock/tegra20-car.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * This header provides constants for binding nvidia,tegra20-car.
0004  *
0005  * The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
0006  * registers. These IDs often match those in the CAR's RST_DEVICES registers,
0007  * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
0008  * this case, those clocks are assigned IDs above 95 in order to highlight
0009  * this issue. Implementations that interpret these clock IDs as bit values
0010  * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
0011  * explicitly handle these special cases.
0012  *
0013  * The balance of the clocks controlled by the CAR are assigned IDs of 96 and
0014  * above.
0015  */
0016
0017 #ifndef _DT_BINDINGS_CLOCK_TEGRA20_CAR_H
0018 #define _DT_BINDINGS_CLOCK_TEGRA20_CAR_H
0019
0020 #define TEGRA20_CLK_CPU 0
0021 /* 1 */
0022 /* 2 */
0023 #define TEGRA20_CLK_AC97 3
0024 #define TEGRA20_CLK_RTC 4
0025 #define TEGRA20_CLK_TIMER 5
0026 #define TEGRA20_CLK_UARTA 6
0027 /* 7 (register bit affects uart2 and vfir) */
0028 #define TEGRA20_CLK_GPIO 8
0029 #define TEGRA20_CLK_SDMMC2 9
0030 /* 10 (register bit affects spdif_in and spdif_out) */
0031 #define TEGRA20_CLK_I2S1 11
0032 #define TEGRA20_CLK_I2C1 12
0033 #define TEGRA20_CLK_NDFLASH 13
0034 #define TEGRA20_CLK_SDMMC1 14
0035 #define TEGRA20_CLK_SDMMC4 15
0036 #define TEGRA20_CLK_TWC 16
0037 #define TEGRA20_CLK_PWM 17
0038 #define TEGRA20_CLK_I2S2 18
0039 #define TEGRA20_CLK_EPP 19
0040 /* 20 (register bit affects vi and vi_sensor) */
0041 #define TEGRA20_CLK_GR2D 21
0042 #define TEGRA20_CLK_USBD 22
0043 #define TEGRA20_CLK_ISP 23
0044 #define TEGRA20_CLK_GR3D 24
0045 #define TEGRA20_CLK_IDE 25
0046 #define TEGRA20_CLK_DISP2 26
0047 #define TEGRA20_CLK_DISP1 27
0048 #define TEGRA20_CLK_HOST1X 28
0049 #define TEGRA20_CLK_VCP 29
0050 /* 30 */
0051 #define TEGRA20_CLK_CACHE2 31
0052
0053 #define TEGRA20_CLK_MC 32
0054 #define TEGRA20_CLK_AHBDMA 33
0055 #define TEGRA20_CLK_APBDMA 34
0056 /* 35 */
0057 #define TEGRA20_CLK_KBC 36
0058 #define TEGRA20_CLK_STAT_MON 37
0059 #define TEGRA20_CLK_PMC 38
0060 #define TEGRA20_CLK_FUSE 39
0061 #define TEGRA20_CLK_KFUSE 40
0062 #define TEGRA20_CLK_SBC1 41
0063 #define TEGRA20_CLK_NOR 42
0064 #define TEGRA20_CLK_SPI 43
0065 #define TEGRA20_CLK_SBC2 44
0066 #define TEGRA20_CLK_XIO 45
0067 #define TEGRA20_CLK_SBC3 46
0068 #define TEGRA20_CLK_DVC 47
0069 #define TEGRA20_CLK_DSI 48
0070 /* 49 (register bit affects tvo and cve) */
0071 #define TEGRA20_CLK_MIPI 50
0072 #define TEGRA20_CLK_HDMI 51
0073 #define TEGRA20_CLK_CSI 52
0074 #define TEGRA20_CLK_TVDAC 53
0075 #define TEGRA20_CLK_I2C2 54
0076 #define TEGRA20_CLK_UARTC 55
0077 /* 56 */
0078 #define TEGRA20_CLK_EMC 57
0079 #define TEGRA20_CLK_USB2 58
0080 #define TEGRA20_CLK_USB3 59
0081 #define TEGRA20_CLK_MPE 60
0082 #define TEGRA20_CLK_VDE 61
0083 #define TEGRA20_CLK_BSEA 62
0084 #define TEGRA20_CLK_BSEV 63
0085
0086 #define TEGRA20_CLK_SPEEDO 64
0087 #define TEGRA20_CLK_UARTD 65
0088 #define TEGRA20_CLK_UARTE 66
0089 #define TEGRA20_CLK_I2C3 67
0090 #define TEGRA20_CLK_SBC4 68
0091 #define TEGRA20_CLK_SDMMC3 69
0092 #define TEGRA20_CLK_PEX 70
0093 #define TEGRA20_CLK_OWR 71
0094 #define TEGRA20_CLK_AFI 72
0095 #define TEGRA20_CLK_CSITE 73
0096 /* 74 */
0097 #define TEGRA20_CLK_AVPUCQ 75
0098 #define TEGRA20_CLK_LA 76
0099 /* 77 */
0100 /* 78 */
0101 /* 79 */
0102 /* 80 */
0103 /* 81 */
0104 /* 82 */
0105 /* 83 */
0106 #define TEGRA20_CLK_IRAMA 84
0107 #define TEGRA20_CLK_IRAMB 85
0108 #define TEGRA20_CLK_IRAMC 86
0109 #define TEGRA20_CLK_IRAMD 87
0110 #define TEGRA20_CLK_CRAM2 88
0111 #define TEGRA20_CLK_AUDIO_2X 89 /* a/k/a audio_2x_sync_clk */
0112 #define TEGRA20_CLK_CLK_D 90
0113 /* 91 */
0114 #define TEGRA20_CLK_CSUS 92
0115 #define TEGRA20_CLK_CDEV2 93
0116 #define TEGRA20_CLK_CDEV1 94
0117 /* 95 */
0118
0119 #define TEGRA20_CLK_UARTB 96
0120 #define TEGRA20_CLK_VFIR 97
0121 #define TEGRA20_CLK_SPDIF_IN 98
0122 #define TEGRA20_CLK_SPDIF_OUT 99
0123 #define TEGRA20_CLK_VI 100
0124 #define TEGRA20_CLK_VI_SENSOR 101
0125 #define TEGRA20_CLK_TVO 102
0126 #define TEGRA20_CLK_CVE 103
0127 #define TEGRA20_CLK_OSC 104
0128 #define TEGRA20_CLK_CLK_32K 105 /* a/k/a clk_s */
0129 #define TEGRA20_CLK_CLK_M 106
0130 #define TEGRA20_CLK_SCLK 107
0131 #define TEGRA20_CLK_CCLK 108
0132 #define TEGRA20_CLK_HCLK 109
0133 #define TEGRA20_CLK_PCLK 110
0134 /* 111 */
0135 #define TEGRA20_CLK_PLL_A 112
0136 #define TEGRA20_CLK_PLL_A_OUT0 113
0137 #define TEGRA20_CLK_PLL_C 114
0138 #define TEGRA20_CLK_PLL_C_OUT1 115
0139 #define TEGRA20_CLK_PLL_D 116
0140 #define TEGRA20_CLK_PLL_D_OUT0 117
0141 #define TEGRA20_CLK_PLL_E 118
0142 #define TEGRA20_CLK_PLL_M 119
0143 #define TEGRA20_CLK_PLL_M_OUT1 120
0144 #define TEGRA20_CLK_PLL_P 121
0145 #define TEGRA20_CLK_PLL_P_OUT1 122
0146 #define TEGRA20_CLK_PLL_P_OUT2 123
0147 #define TEGRA20_CLK_PLL_P_OUT3 124
0148 #define TEGRA20_CLK_PLL_P_OUT4 125
0149 #define TEGRA20_CLK_PLL_S 126
0150 #define TEGRA20_CLK_PLL_U 127
0151
0152 #define TEGRA20_CLK_PLL_X 128
0153 #define TEGRA20_CLK_COP 129 /* a/k/a avp */
0154 #define TEGRA20_CLK_AUDIO 130 /* a/k/a audio_sync_clk */
0155 #define TEGRA20_CLK_PLL_REF 131
0156 #define TEGRA20_CLK_TWD 132
0157 #define TEGRA20_CLK_CLK_MAX 133
0158
0159 #endif  /* _DT_BINDINGS_CLOCK_TEGRA20_CAR_H */