OSCL-LXR |
|
|
|
|||
0001 /* SPDX-License-Identifier: GPL-2.0 */ 0002 /** @file */ 0003 0004 #ifndef _MACH_T186_CLK_T186_H 0005 #define _MACH_T186_CLK_T186_H 0006 0007 /** 0008 * @defgroup clock_ids Clock Identifiers 0009 * @{ 0010 * @defgroup extern_input external input clocks 0011 * @{ 0012 * @def TEGRA186_CLK_OSC 0013 * @def TEGRA186_CLK_CLK_32K 0014 * @def TEGRA186_CLK_DTV_INPUT 0015 * @def TEGRA186_CLK_SOR0_PAD_CLKOUT 0016 * @def TEGRA186_CLK_SOR1_PAD_CLKOUT 0017 * @def TEGRA186_CLK_I2S1_SYNC_INPUT 0018 * @def TEGRA186_CLK_I2S2_SYNC_INPUT 0019 * @def TEGRA186_CLK_I2S3_SYNC_INPUT 0020 * @def TEGRA186_CLK_I2S4_SYNC_INPUT 0021 * @def TEGRA186_CLK_I2S5_SYNC_INPUT 0022 * @def TEGRA186_CLK_I2S6_SYNC_INPUT 0023 * @def TEGRA186_CLK_SPDIFIN_SYNC_INPUT 0024 * @} 0025 * 0026 * @defgroup extern_output external output clocks 0027 * @{ 0028 * @def TEGRA186_CLK_EXTPERIPH1 0029 * @def TEGRA186_CLK_EXTPERIPH2 0030 * @def TEGRA186_CLK_EXTPERIPH3 0031 * @def TEGRA186_CLK_EXTPERIPH4 0032 * @} 0033 * 0034 * @defgroup display_clks display related clocks 0035 * @{ 0036 * @def TEGRA186_CLK_CEC 0037 * @def TEGRA186_CLK_DSIC 0038 * @def TEGRA186_CLK_DSIC_LP 0039 * @def TEGRA186_CLK_DSID 0040 * @def TEGRA186_CLK_DSID_LP 0041 * @def TEGRA186_CLK_DPAUX1 0042 * @def TEGRA186_CLK_DPAUX 0043 * @def TEGRA186_CLK_HDA2HDMICODEC 0044 * @def TEGRA186_CLK_NVDISPLAY_DISP 0045 * @def TEGRA186_CLK_NVDISPLAY_DSC 0046 * @def TEGRA186_CLK_NVDISPLAY_P0 0047 * @def TEGRA186_CLK_NVDISPLAY_P1 0048 * @def TEGRA186_CLK_NVDISPLAY_P2 0049 * @def TEGRA186_CLK_NVDISPLAYHUB 0050 * @def TEGRA186_CLK_SOR_SAFE 0051 * @def TEGRA186_CLK_SOR0 0052 * @def TEGRA186_CLK_SOR0_OUT 0053 * @def TEGRA186_CLK_SOR1 0054 * @def TEGRA186_CLK_SOR1_OUT 0055 * @def TEGRA186_CLK_DSI 0056 * @def TEGRA186_CLK_MIPI_CAL 0057 * @def TEGRA186_CLK_DSIA_LP 0058 * @def TEGRA186_CLK_DSIB 0059 * @def TEGRA186_CLK_DSIB_LP 0060 * @} 0061 * 0062 * @defgroup camera_clks camera related clocks 0063 * @{ 0064 * @def TEGRA186_CLK_NVCSI 0065 * @def TEGRA186_CLK_NVCSILP 0066 * @def TEGRA186_CLK_VI 0067 * @} 0068 * 0069 * @defgroup audio_clks audio related clocks 0070 * @{ 0071 * @def TEGRA186_CLK_ACLK 0072 * @def TEGRA186_CLK_ADSP 0073 * @def TEGRA186_CLK_ADSPNEON 0074 * @def TEGRA186_CLK_AHUB 0075 * @def TEGRA186_CLK_APE 0076 * @def TEGRA186_CLK_APB2APE 0077 * @def TEGRA186_CLK_AUD_MCLK 0078 * @def TEGRA186_CLK_DMIC1 0079 * @def TEGRA186_CLK_DMIC2 0080 * @def TEGRA186_CLK_DMIC3 0081 * @def TEGRA186_CLK_DMIC4 0082 * @def TEGRA186_CLK_DSPK1 0083 * @def TEGRA186_CLK_DSPK2 0084 * @def TEGRA186_CLK_HDA 0085 * @def TEGRA186_CLK_HDA2CODEC_2X 0086 * @def TEGRA186_CLK_I2S1 0087 * @def TEGRA186_CLK_I2S2 0088 * @def TEGRA186_CLK_I2S3 0089 * @def TEGRA186_CLK_I2S4 0090 * @def TEGRA186_CLK_I2S5 0091 * @def TEGRA186_CLK_I2S6 0092 * @def TEGRA186_CLK_MAUD 0093 * @def TEGRA186_CLK_PLL_A_OUT0 0094 * @def TEGRA186_CLK_SPDIF_DOUBLER 0095 * @def TEGRA186_CLK_SPDIF_IN 0096 * @def TEGRA186_CLK_SPDIF_OUT 0097 * @def TEGRA186_CLK_SYNC_DMIC1 0098 * @def TEGRA186_CLK_SYNC_DMIC2 0099 * @def TEGRA186_CLK_SYNC_DMIC3 0100 * @def TEGRA186_CLK_SYNC_DMIC4 0101 * @def TEGRA186_CLK_SYNC_DMIC5 0102 * @def TEGRA186_CLK_SYNC_DSPK1 0103 * @def TEGRA186_CLK_SYNC_DSPK2 0104 * @def TEGRA186_CLK_SYNC_I2S1 0105 * @def TEGRA186_CLK_SYNC_I2S2 0106 * @def TEGRA186_CLK_SYNC_I2S3 0107 * @def TEGRA186_CLK_SYNC_I2S4 0108 * @def TEGRA186_CLK_SYNC_I2S5 0109 * @def TEGRA186_CLK_SYNC_I2S6 0110 * @def TEGRA186_CLK_SYNC_SPDIF 0111 * @} 0112 * 0113 * @defgroup uart_clks UART clocks 0114 * @{ 0115 * @def TEGRA186_CLK_AON_UART_FST_MIPI_CAL 0116 * @def TEGRA186_CLK_UARTA 0117 * @def TEGRA186_CLK_UARTB 0118 * @def TEGRA186_CLK_UARTC 0119 * @def TEGRA186_CLK_UARTD 0120 * @def TEGRA186_CLK_UARTE 0121 * @def TEGRA186_CLK_UARTF 0122 * @def TEGRA186_CLK_UARTG 0123 * @def TEGRA186_CLK_UART_FST_MIPI_CAL 0124 * @} 0125 * 0126 * @defgroup i2c_clks I2C clocks 0127 * @{ 0128 * @def TEGRA186_CLK_AON_I2C_SLOW 0129 * @def TEGRA186_CLK_I2C1 0130 * @def TEGRA186_CLK_I2C2 0131 * @def TEGRA186_CLK_I2C3 0132 * @def TEGRA186_CLK_I2C4 0133 * @def TEGRA186_CLK_I2C5 0134 * @def TEGRA186_CLK_I2C6 0135 * @def TEGRA186_CLK_I2C8 0136 * @def TEGRA186_CLK_I2C9 0137 * @def TEGRA186_CLK_I2C1 0138 * @def TEGRA186_CLK_I2C12 0139 * @def TEGRA186_CLK_I2C13 0140 * @def TEGRA186_CLK_I2C14 0141 * @def TEGRA186_CLK_I2C_SLOW 0142 * @def TEGRA186_CLK_VI_I2C 0143 * @} 0144 * 0145 * @defgroup spi_clks SPI clocks 0146 * @{ 0147 * @def TEGRA186_CLK_SPI1 0148 * @def TEGRA186_CLK_SPI2 0149 * @def TEGRA186_CLK_SPI3 0150 * @def TEGRA186_CLK_SPI4 0151 * @} 0152 * 0153 * @defgroup storage storage related clocks 0154 * @{ 0155 * @def TEGRA186_CLK_SATA 0156 * @def TEGRA186_CLK_SATA_OOB 0157 * @def TEGRA186_CLK_SATA_IOBIST 0158 * @def TEGRA186_CLK_SDMMC_LEGACY_TM 0159 * @def TEGRA186_CLK_SDMMC1 0160 * @def TEGRA186_CLK_SDMMC2 0161 * @def TEGRA186_CLK_SDMMC3 0162 * @def TEGRA186_CLK_SDMMC4 0163 * @def TEGRA186_CLK_QSPI 0164 * @def TEGRA186_CLK_QSPI_OUT 0165 * @def TEGRA186_CLK_UFSDEV_REF 0166 * @def TEGRA186_CLK_UFSHC 0167 * @} 0168 * 0169 * @defgroup pwm_clks PWM clocks 0170 * @{ 0171 * @def TEGRA186_CLK_PWM1 0172 * @def TEGRA186_CLK_PWM2 0173 * @def TEGRA186_CLK_PWM3 0174 * @def TEGRA186_CLK_PWM4 0175 * @def TEGRA186_CLK_PWM5 0176 * @def TEGRA186_CLK_PWM6 0177 * @def TEGRA186_CLK_PWM7 0178 * @def TEGRA186_CLK_PWM8 0179 * @} 0180 * 0181 * @defgroup plls PLLs and related clocks 0182 * @{ 0183 * @def TEGRA186_CLK_PLLREFE_OUT_GATED 0184 * @def TEGRA186_CLK_PLLREFE_OUT1 0185 * @def TEGRA186_CLK_PLLD_OUT1 0186 * @def TEGRA186_CLK_PLLP_OUT0 0187 * @def TEGRA186_CLK_PLLP_OUT5 0188 * @def TEGRA186_CLK_PLLA 0189 * @def TEGRA186_CLK_PLLE_PWRSEQ 0190 * @def TEGRA186_CLK_PLLA_OUT1 0191 * @def TEGRA186_CLK_PLLREFE_REF 0192 * @def TEGRA186_CLK_UPHY_PLL0_PWRSEQ 0193 * @def TEGRA186_CLK_UPHY_PLL1_PWRSEQ 0194 * @def TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH 0195 * @def TEGRA186_CLK_PLLREFE_PEX 0196 * @def TEGRA186_CLK_PLLREFE_IDDQ 0197 * @def TEGRA186_CLK_PLLC_OUT_AON 0198 * @def TEGRA186_CLK_PLLC_OUT_ISP 0199 * @def TEGRA186_CLK_PLLC_OUT_VE 0200 * @def TEGRA186_CLK_PLLC4_OUT 0201 * @def TEGRA186_CLK_PLLREFE_OUT 0202 * @def TEGRA186_CLK_PLLREFE_PLL_REF 0203 * @def TEGRA186_CLK_PLLE 0204 * @def TEGRA186_CLK_PLLC 0205 * @def TEGRA186_CLK_PLLP 0206 * @def TEGRA186_CLK_PLLD 0207 * @def TEGRA186_CLK_PLLD2 0208 * @def TEGRA186_CLK_PLLREFE_VCO 0209 * @def TEGRA186_CLK_PLLC2 0210 * @def TEGRA186_CLK_PLLC3 0211 * @def TEGRA186_CLK_PLLDP 0212 * @def TEGRA186_CLK_PLLC4_VCO 0213 * @def TEGRA186_CLK_PLLA1 0214 * @def TEGRA186_CLK_PLLNVCSI 0215 * @def TEGRA186_CLK_PLLDISPHUB 0216 * @def TEGRA186_CLK_PLLD3 0217 * @def TEGRA186_CLK_PLLBPMPCAM 0218 * @def TEGRA186_CLK_PLLAON 0219 * @def TEGRA186_CLK_PLLU 0220 * @def TEGRA186_CLK_PLLC4_VCO_DIV2 0221 * @def TEGRA186_CLK_PLL_REF 0222 * @def TEGRA186_CLK_PLLREFE_OUT1_DIV5 0223 * @def TEGRA186_CLK_UTMIP_PLL_PWRSEQ 0224 * @def TEGRA186_CLK_PLL_U_48M 0225 * @def TEGRA186_CLK_PLL_U_480M 0226 * @def TEGRA186_CLK_PLLC4_OUT0 0227 * @def TEGRA186_CLK_PLLC4_OUT1 0228 * @def TEGRA186_CLK_PLLC4_OUT2 0229 * @def TEGRA186_CLK_PLLC4_OUT_MUX 0230 * @def TEGRA186_CLK_DFLLDISP_DIV 0231 * @def TEGRA186_CLK_PLLDISPHUB_DIV 0232 * @def TEGRA186_CLK_PLLP_DIV8 0233 * @} 0234 * 0235 * @defgroup nafll_clks NAFLL clock sources 0236 * @{ 0237 * @def TEGRA186_CLK_NAFLL_AXI_CBB 0238 * @def TEGRA186_CLK_NAFLL_BCPU 0239 * @def TEGRA186_CLK_NAFLL_BPMP 0240 * @def TEGRA186_CLK_NAFLL_DISP 0241 * @def TEGRA186_CLK_NAFLL_GPU 0242 * @def TEGRA186_CLK_NAFLL_ISP 0243 * @def TEGRA186_CLK_NAFLL_MCPU 0244 * @def TEGRA186_CLK_NAFLL_NVDEC 0245 * @def TEGRA186_CLK_NAFLL_NVENC 0246 * @def TEGRA186_CLK_NAFLL_NVJPG 0247 * @def TEGRA186_CLK_NAFLL_SCE 0248 * @def TEGRA186_CLK_NAFLL_SE 0249 * @def TEGRA186_CLK_NAFLL_TSEC 0250 * @def TEGRA186_CLK_NAFLL_TSECB 0251 * @def TEGRA186_CLK_NAFLL_VI 0252 * @def TEGRA186_CLK_NAFLL_VIC 0253 * @} 0254 * 0255 * @defgroup mphy MPHY related clocks 0256 * @{ 0257 * @def TEGRA186_CLK_MPHY_L0_RX_SYMB 0258 * @def TEGRA186_CLK_MPHY_L0_RX_LS_BIT 0259 * @def TEGRA186_CLK_MPHY_L0_TX_SYMB 0260 * @def TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT 0261 * @def TEGRA186_CLK_MPHY_L0_RX_ANA 0262 * @def TEGRA186_CLK_MPHY_L1_RX_ANA 0263 * @def TEGRA186_CLK_MPHY_IOBIST 0264 * @def TEGRA186_CLK_MPHY_TX_1MHZ_REF 0265 * @def TEGRA186_CLK_MPHY_CORE_PLL_FIXED 0266 * @} 0267 * 0268 * @defgroup eavb EAVB related clocks 0269 * @{ 0270 * @def TEGRA186_CLK_EQOS_AXI 0271 * @def TEGRA186_CLK_EQOS_PTP_REF 0272 * @def TEGRA186_CLK_EQOS_RX 0273 * @def TEGRA186_CLK_EQOS_RX_INPUT 0274 * @def TEGRA186_CLK_EQOS_TX 0275 * @} 0276 * 0277 * @defgroup usb USB related clocks 0278 * @{ 0279 * @def TEGRA186_CLK_PEX_USB_PAD0_MGMT 0280 * @def TEGRA186_CLK_PEX_USB_PAD1_MGMT 0281 * @def TEGRA186_CLK_HSIC_TRK 0282 * @def TEGRA186_CLK_USB2_TRK 0283 * @def TEGRA186_CLK_USB2_HSIC_TRK 0284 * @def TEGRA186_CLK_XUSB_CORE_SS 0285 * @def TEGRA186_CLK_XUSB_CORE_DEV 0286 * @def TEGRA186_CLK_XUSB_FALCON 0287 * @def TEGRA186_CLK_XUSB_FS 0288 * @def TEGRA186_CLK_XUSB 0289 * @def TEGRA186_CLK_XUSB_DEV 0290 * @def TEGRA186_CLK_XUSB_HOST 0291 * @def TEGRA186_CLK_XUSB_SS 0292 * @} 0293 * 0294 * @defgroup bigblock compute block related clocks 0295 * @{ 0296 * @def TEGRA186_CLK_GPCCLK 0297 * @def TEGRA186_CLK_GPC2CLK 0298 * @def TEGRA186_CLK_GPU 0299 * @def TEGRA186_CLK_HOST1X 0300 * @def TEGRA186_CLK_ISP 0301 * @def TEGRA186_CLK_NVDEC 0302 * @def TEGRA186_CLK_NVENC 0303 * @def TEGRA186_CLK_NVJPG 0304 * @def TEGRA186_CLK_SE 0305 * @def TEGRA186_CLK_TSEC 0306 * @def TEGRA186_CLK_TSECB 0307 * @def TEGRA186_CLK_VIC 0308 * @} 0309 * 0310 * @defgroup can CAN bus related clocks 0311 * @{ 0312 * @def TEGRA186_CLK_CAN1 0313 * @def TEGRA186_CLK_CAN1_HOST 0314 * @def TEGRA186_CLK_CAN2 0315 * @def TEGRA186_CLK_CAN2_HOST 0316 * @} 0317 * 0318 * @defgroup system basic system clocks 0319 * @{ 0320 * @def TEGRA186_CLK_ACTMON 0321 * @def TEGRA186_CLK_AON_APB 0322 * @def TEGRA186_CLK_AON_CPU_NIC 0323 * @def TEGRA186_CLK_AON_NIC 0324 * @def TEGRA186_CLK_AXI_CBB 0325 * @def TEGRA186_CLK_BPMP_APB 0326 * @def TEGRA186_CLK_BPMP_CPU_NIC 0327 * @def TEGRA186_CLK_BPMP_NIC_RATE 0328 * @def TEGRA186_CLK_CLK_M 0329 * @def TEGRA186_CLK_EMC 0330 * @def TEGRA186_CLK_MSS_ENCRYPT 0331 * @def TEGRA186_CLK_SCE_APB 0332 * @def TEGRA186_CLK_SCE_CPU_NIC 0333 * @def TEGRA186_CLK_SCE_NIC 0334 * @def TEGRA186_CLK_TSC 0335 * @} 0336 * 0337 * @defgroup pcie_clks PCIe related clocks 0338 * @{ 0339 * @def TEGRA186_CLK_AFI 0340 * @def TEGRA186_CLK_PCIE 0341 * @def TEGRA186_CLK_PCIE2_IOBIST 0342 * @def TEGRA186_CLK_PCIERX0 0343 * @def TEGRA186_CLK_PCIERX1 0344 * @def TEGRA186_CLK_PCIERX2 0345 * @def TEGRA186_CLK_PCIERX3 0346 * @def TEGRA186_CLK_PCIERX4 0347 * @} 0348 */ 0349 0350 /** @brief output of gate CLK_ENB_FUSE */ 0351 #define TEGRA186_CLK_FUSE 0 0352 /** 0353 * @brief It's not what you think 0354 * @details output of gate CLK_ENB_GPU. This output connects to the GPU 0355 * pwrclk. @warning: This is almost certainly not the clock you think 0356 * it is. If you're looking for the clock of the graphics engine, see 0357 * TEGRA186_GPCCLK 0358 */ 0359 #define TEGRA186_CLK_GPU 1 0360 /** @brief output of gate CLK_ENB_PCIE */ 0361 #define TEGRA186_CLK_PCIE 3 0362 /** @brief output of the divider IPFS_CLK_DIVISOR */ 0363 #define TEGRA186_CLK_AFI 4 0364 /** @brief output of gate CLK_ENB_PCIE2_IOBIST */ 0365 #define TEGRA186_CLK_PCIE2_IOBIST 5 0366 /** @brief output of gate CLK_ENB_PCIERX0*/ 0367 #define TEGRA186_CLK_PCIERX0 6 0368 /** @brief output of gate CLK_ENB_PCIERX1*/ 0369 #define TEGRA186_CLK_PCIERX1 7 0370 /** @brief output of gate CLK_ENB_PCIERX2*/ 0371 #define TEGRA186_CLK_PCIERX2 8 0372 /** @brief output of gate CLK_ENB_PCIERX3*/ 0373 #define TEGRA186_CLK_PCIERX3 9 0374 /** @brief output of gate CLK_ENB_PCIERX4*/ 0375 #define TEGRA186_CLK_PCIERX4 10 0376 /** @brief output branch of PLL_C for ISP, controlled by gate CLK_ENB_PLLC_OUT_ISP */ 0377 #define TEGRA186_CLK_PLLC_OUT_ISP 11 0378 /** @brief output branch of PLL_C for VI, controlled by gate CLK_ENB_PLLC_OUT_VE */ 0379 #define TEGRA186_CLK_PLLC_OUT_VE 12 0380 /** @brief output branch of PLL_C for AON domain, controlled by gate CLK_ENB_PLLC_OUT_AON */ 0381 #define TEGRA186_CLK_PLLC_OUT_AON 13 0382 /** @brief output of gate CLK_ENB_SOR_SAFE */ 0383 #define TEGRA186_CLK_SOR_SAFE 39 0384 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */ 0385 #define TEGRA186_CLK_I2S2 42 0386 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */ 0387 #define TEGRA186_CLK_I2S3 43 0388 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDF_IN */ 0389 #define TEGRA186_CLK_SPDIF_IN 44 0390 /** @brief output of gate CLK_ENB_SPDIF_DOUBLER */ 0391 #define TEGRA186_CLK_SPDIF_DOUBLER 45 0392 /** @clkdesc{spi_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_SPI3} */ 0393 #define TEGRA186_CLK_SPI3 46 0394 /** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1} */ 0395 #define TEGRA186_CLK_I2C1 47 0396 /** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5} */ 0397 #define TEGRA186_CLK_I2C5 48 0398 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */ 0399 #define TEGRA186_CLK_SPI1 49 0400 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */ 0401 #define TEGRA186_CLK_ISP 50 0402 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */ 0403 #define TEGRA186_CLK_VI 51 0404 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */ 0405 #define TEGRA186_CLK_SDMMC1 52 0406 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 */ 0407 #define TEGRA186_CLK_SDMMC2 53 0408 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ 0409 #define TEGRA186_CLK_SDMMC4 54 0410 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ 0411 #define TEGRA186_CLK_UARTA 55 0412 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTB */ 0413 #define TEGRA186_CLK_UARTB 56 0414 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */ 0415 #define TEGRA186_CLK_HOST1X 57 0416 /** 0417 * @brief controls the EMC clock frequency. 0418 * @details Doing a clk_set_rate on this clock will select the 0419 * appropriate clock source, program the source rate and execute a 0420 * specific sequence to switch to the new clock source for both memory 0421 * controllers. This can be used to control the balance between memory 0422 * throughput and memory controller power. 0423 */ 0424 #define TEGRA186_CLK_EMC 58 0425 /* @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4 */ 0426 #define TEGRA186_CLK_EXTPERIPH4 73 0427 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI4 */ 0428 #define TEGRA186_CLK_SPI4 74 0429 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */ 0430 #define TEGRA186_CLK_I2C3 75 0431 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 */ 0432 #define TEGRA186_CLK_SDMMC3 76 0433 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTD */ 0434 #define TEGRA186_CLK_UARTD 77 0435 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */ 0436 #define TEGRA186_CLK_I2S1 79 0437 /** output of gate CLK_ENB_DTV */ 0438 #define TEGRA186_CLK_DTV 80 0439 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSEC */ 0440 #define TEGRA186_CLK_TSEC 81 0441 /** @brief output of gate CLK_ENB_DP2 */ 0442 #define TEGRA186_CLK_DP2 82 0443 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */ 0444 #define TEGRA186_CLK_I2S4 84 0445 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */ 0446 #define TEGRA186_CLK_I2S5 85 0447 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */ 0448 #define TEGRA186_CLK_I2C4 86 0449 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */ 0450 #define TEGRA186_CLK_AHUB 87 0451 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X */ 0452 #define TEGRA186_CLK_HDA2CODEC_2X 88 0453 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 */ 0454 #define TEGRA186_CLK_EXTPERIPH1 89 0455 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2 */ 0456 #define TEGRA186_CLK_EXTPERIPH2 90 0457 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3 */ 0458 #define TEGRA186_CLK_EXTPERIPH3 91 0459 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW */ 0460 #define TEGRA186_CLK_I2C_SLOW 92 0461 /** @brief output of the SOR1_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */ 0462 #define TEGRA186_CLK_SOR1 93 0463 /** @brief output of gate CLK_ENB_CEC */ 0464 #define TEGRA186_CLK_CEC 94 0465 /** @brief output of gate CLK_ENB_DPAUX1 */ 0466 #define TEGRA186_CLK_DPAUX1 95 0467 /** @brief output of gate CLK_ENB_DPAUX */ 0468 #define TEGRA186_CLK_DPAUX 96 0469 /** @brief output of the SOR0_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */ 0470 #define TEGRA186_CLK_SOR0 97 0471 /** @brief output of gate CLK_ENB_HDA2HDMICODEC */ 0472 #define TEGRA186_CLK_HDA2HDMICODEC 98 0473 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SATA */ 0474 #define TEGRA186_CLK_SATA 99 0475 /** @brief output of gate CLK_ENB_SATA_OOB */ 0476 #define TEGRA186_CLK_SATA_OOB 100 0477 /** @brief output of gate CLK_ENB_SATA_IOBIST */ 0478 #define TEGRA186_CLK_SATA_IOBIST 101 0479 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA */ 0480 #define TEGRA186_CLK_HDA 102 0481 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SE */ 0482 #define TEGRA186_CLK_SE 103 0483 /** @brief output of gate CLK_ENB_APB2APE */ 0484 #define TEGRA186_CLK_APB2APE 104 0485 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */ 0486 #define TEGRA186_CLK_APE 105 0487 /** @brief output of gate CLK_ENB_IQC1 */ 0488 #define TEGRA186_CLK_IQC1 106 0489 /** @brief output of gate CLK_ENB_IQC2 */ 0490 #define TEGRA186_CLK_IQC2 107 0491 /** divide by 2 version of TEGRA186_CLK_PLLREFE_VCO */ 0492 #define TEGRA186_CLK_PLLREFE_OUT 108 0493 /** @brief output of gate CLK_ENB_PLLREFE_PLL_REF */ 0494 #define TEGRA186_CLK_PLLREFE_PLL_REF 109 0495 /** @brief output of gate CLK_ENB_PLLC4_OUT */ 0496 #define TEGRA186_CLK_PLLC4_OUT 110 0497 /** @brief output of mux xusb_core_clk_switch on page 67 of T186_Clocks_IAS.doc */ 0498 #define TEGRA186_CLK_XUSB 111 0499 /** controls xusb_dev_ce signal on page 66 and 67 of T186_Clocks_IAS.doc */ 0500 #define TEGRA186_CLK_XUSB_DEV 112 0501 /** controls xusb_host_ce signal on page 67 of T186_Clocks_IAS.doc */ 0502 #define TEGRA186_CLK_XUSB_HOST 113 0503 /** controls xusb_ss_ce signal on page 67 of T186_Clocks_IAS.doc */ 0504 #define TEGRA186_CLK_XUSB_SS 114 0505 /** @brief output of gate CLK_ENB_DSI */ 0506 #define TEGRA186_CLK_DSI 115 0507 /** @brief output of gate CLK_ENB_MIPI_CAL */ 0508 #define TEGRA186_CLK_MIPI_CAL 116 0509 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP */ 0510 #define TEGRA186_CLK_DSIA_LP 117 0511 /** @brief output of gate CLK_ENB_DSIB */ 0512 #define TEGRA186_CLK_DSIB 118 0513 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP */ 0514 #define TEGRA186_CLK_DSIB_LP 119 0515 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */ 0516 #define TEGRA186_CLK_DMIC1 122 0517 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */ 0518 #define TEGRA186_CLK_DMIC2 123 0519 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */ 0520 #define TEGRA186_CLK_AUD_MCLK 124 0521 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */ 0522 #define TEGRA186_CLK_I2C6 125 0523 /**output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL */ 0524 #define TEGRA186_CLK_UART_FST_MIPI_CAL 126 0525 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */ 0526 #define TEGRA186_CLK_VIC 127 0527 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM */ 0528 #define TEGRA186_CLK_SDMMC_LEGACY_TM 128 0529 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC */ 0530 #define TEGRA186_CLK_NVDEC 129 0531 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG */ 0532 #define TEGRA186_CLK_NVJPG 130 0533 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVENC */ 0534 #define TEGRA186_CLK_NVENC 131 0535 /** @brief output of the QSPI_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */ 0536 #define TEGRA186_CLK_QSPI 132 0537 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C */ 0538 #define TEGRA186_CLK_VI_I2C 133 0539 /** @brief output of gate CLK_ENB_HSIC_TRK */ 0540 #define TEGRA186_CLK_HSIC_TRK 134 0541 /** @brief output of gate CLK_ENB_USB2_TRK */ 0542 #define TEGRA186_CLK_USB2_TRK 135 0543 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MAUD */ 0544 #define TEGRA186_CLK_MAUD 136 0545 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSECB */ 0546 #define TEGRA186_CLK_TSECB 137 0547 /** @brief output of gate CLK_ENB_ADSP */ 0548 #define TEGRA186_CLK_ADSP 138 0549 /** @brief output of gate CLK_ENB_ADSPNEON */ 0550 #define TEGRA186_CLK_ADSPNEON 139 0551 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB */ 0552 #define TEGRA186_CLK_MPHY_L0_RX_SYMB 140 0553 /** @brief output of gate CLK_ENB_MPHY_L0_RX_LS_BIT */ 0554 #define TEGRA186_CLK_MPHY_L0_RX_LS_BIT 141 0555 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB */ 0556 #define TEGRA186_CLK_MPHY_L0_TX_SYMB 142 0557 /** @brief output of gate CLK_ENB_MPHY_L0_TX_LS_3XBIT */ 0558 #define TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT 143 0559 /** @brief output of gate CLK_ENB_MPHY_L0_RX_ANA */ 0560 #define TEGRA186_CLK_MPHY_L0_RX_ANA 144 0561 /** @brief output of gate CLK_ENB_MPHY_L1_RX_ANA */ 0562 #define TEGRA186_CLK_MPHY_L1_RX_ANA 145 0563 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST */ 0564 #define TEGRA186_CLK_MPHY_IOBIST 146 0565 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF */ 0566 #define TEGRA186_CLK_MPHY_TX_1MHZ_REF 147 0567 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED */ 0568 #define TEGRA186_CLK_MPHY_CORE_PLL_FIXED 148 0569 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */ 0570 #define TEGRA186_CLK_AXI_CBB 149 0571 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */ 0572 #define TEGRA186_CLK_DMIC3 150 0573 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */ 0574 #define TEGRA186_CLK_DMIC4 151 0575 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */ 0576 #define TEGRA186_CLK_DSPK1 152 0577 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */ 0578 #define TEGRA186_CLK_DSPK2 153 0579 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */ 0580 #define TEGRA186_CLK_I2S6 154 0581 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0 */ 0582 #define TEGRA186_CLK_NVDISPLAY_P0 155 0583 /** @brief output of the NVDISPLAY_DISP_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP */ 0584 #define TEGRA186_CLK_NVDISPLAY_DISP 156 0585 /** @brief output of gate CLK_ENB_NVDISPLAY_DSC */ 0586 #define TEGRA186_CLK_NVDISPLAY_DSC 157 0587 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB */ 0588 #define TEGRA186_CLK_NVDISPLAYHUB 158 0589 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1 */ 0590 #define TEGRA186_CLK_NVDISPLAY_P1 159 0591 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2 */ 0592 #define TEGRA186_CLK_NVDISPLAY_P2 160 0593 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH */ 0594 #define TEGRA186_CLK_TACH 166 0595 /** @brief output of gate CLK_ENB_EQOS */ 0596 #define TEGRA186_CLK_EQOS_AXI 167 0597 /** @brief output of gate CLK_ENB_EQOS_RX */ 0598 #define TEGRA186_CLK_EQOS_RX 168 0599 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS */ 0600 #define TEGRA186_CLK_UFSHC 178 0601 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF */ 0602 #define TEGRA186_CLK_UFSDEV_REF 179 0603 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI */ 0604 #define TEGRA186_CLK_NVCSI 180 0605 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP */ 0606 #define TEGRA186_CLK_NVCSILP 181 0607 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */ 0608 #define TEGRA186_CLK_I2C7 182 0609 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */ 0610 #define TEGRA186_CLK_I2C9 183 0611 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C12 */ 0612 #define TEGRA186_CLK_I2C12 184 0613 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C13 */ 0614 #define TEGRA186_CLK_I2C13 185 0615 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C14 */ 0616 #define TEGRA186_CLK_I2C14 186 0617 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */ 0618 #define TEGRA186_CLK_PWM1 187 0619 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */ 0620 #define TEGRA186_CLK_PWM2 188 0621 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */ 0622 #define TEGRA186_CLK_PWM3 189 0623 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */ 0624 #define TEGRA186_CLK_PWM5 190 0625 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */ 0626 #define TEGRA186_CLK_PWM6 191 0627 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */ 0628 #define TEGRA186_CLK_PWM7 192 0629 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */ 0630 #define TEGRA186_CLK_PWM8 193 0631 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTE */ 0632 #define TEGRA186_CLK_UARTE 194 0633 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTF */ 0634 #define TEGRA186_CLK_UARTF 195 0635 /** @deprecated */ 0636 #define TEGRA186_CLK_DBGAPB 196 0637 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC */ 0638 #define TEGRA186_CLK_BPMP_CPU_NIC 197 0639 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB */ 0640 #define TEGRA186_CLK_BPMP_APB 199 0641 /** @brief output of mux controlled by TEGRA186_CLK_SOC_ACTMON */ 0642 #define TEGRA186_CLK_ACTMON 201 0643 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC */ 0644 #define TEGRA186_CLK_AON_CPU_NIC 208 0645 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */ 0646 #define TEGRA186_CLK_CAN1 210 0647 /** @brief output of gate CLK_ENB_CAN1_HOST */ 0648 #define TEGRA186_CLK_CAN1_HOST 211 0649 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */ 0650 #define TEGRA186_CLK_CAN2 212 0651 /** @brief output of gate CLK_ENB_CAN2_HOST */ 0652 #define TEGRA186_CLK_CAN2_HOST 213 0653 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB */ 0654 #define TEGRA186_CLK_AON_APB 214 0655 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTC */ 0656 #define TEGRA186_CLK_UARTC 215 0657 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTG */ 0658 #define TEGRA186_CLK_UARTG 216 0659 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL */ 0660 #define TEGRA186_CLK_AON_UART_FST_MIPI_CAL 217 0661 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */ 0662 #define TEGRA186_CLK_I2C2 218 0663 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */ 0664 #define TEGRA186_CLK_I2C8 219 0665 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C10 */ 0666 #define TEGRA186_CLK_I2C10 220 0667 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW */ 0668 #define TEGRA186_CLK_AON_I2C_SLOW 221 0669 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI2 */ 0670 #define TEGRA186_CLK_SPI2 222 0671 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5 */ 0672 #define TEGRA186_CLK_DMIC5 223 0673 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH */ 0674 #define TEGRA186_CLK_AON_TOUCH 224 0675 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */ 0676 #define TEGRA186_CLK_PWM4 225 0677 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSC. This clock object is read only and is used for all timers in the system. */ 0678 #define TEGRA186_CLK_TSC 226 0679 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT */ 0680 #define TEGRA186_CLK_MSS_ENCRYPT 227 0681 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC */ 0682 #define TEGRA186_CLK_SCE_CPU_NIC 228 0683 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB */ 0684 #define TEGRA186_CLK_SCE_APB 230 0685 /** @brief output of gate CLK_ENB_DSIC */ 0686 #define TEGRA186_CLK_DSIC 231 0687 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP */ 0688 #define TEGRA186_CLK_DSIC_LP 232 0689 /** @brief output of gate CLK_ENB_DSID */ 0690 #define TEGRA186_CLK_DSID 233 0691 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP */ 0692 #define TEGRA186_CLK_DSID_LP 234 0693 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP */ 0694 #define TEGRA186_CLK_PEX_SATA_USB_RX_BYP 236 0695 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT */ 0696 #define TEGRA186_CLK_SPDIF_OUT 238 0697 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 */ 0698 #define TEGRA186_CLK_EQOS_PTP_REF 239 0699 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK */ 0700 #define TEGRA186_CLK_EQOS_TX 240 0701 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK */ 0702 #define TEGRA186_CLK_USB2_HSIC_TRK 241 0703 /** @brief output of mux xusb_ss_clk_switch on page 66 of T186_Clocks_IAS.doc */ 0704 #define TEGRA186_CLK_XUSB_CORE_SS 242 0705 /** @brief output of mux xusb_core_dev_clk_switch on page 67 of T186_Clocks_IAS.doc */ 0706 #define TEGRA186_CLK_XUSB_CORE_DEV 243 0707 /** @brief output of mux xusb_core_falcon_clk_switch on page 67 of T186_Clocks_IAS.doc */ 0708 #define TEGRA186_CLK_XUSB_FALCON 244 0709 /** @brief output of mux xusb_fs_clk_switch on page 66 of T186_Clocks_IAS.doc */ 0710 #define TEGRA186_CLK_XUSB_FS 245 0711 /** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */ 0712 #define TEGRA186_CLK_PLL_A_OUT0 246 0713 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */ 0714 #define TEGRA186_CLK_SYNC_I2S1 247 0715 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */ 0716 #define TEGRA186_CLK_SYNC_I2S2 248 0717 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */ 0718 #define TEGRA186_CLK_SYNC_I2S3 249 0719 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */ 0720 #define TEGRA186_CLK_SYNC_I2S4 250 0721 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */ 0722 #define TEGRA186_CLK_SYNC_I2S5 251 0723 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */ 0724 #define TEGRA186_CLK_SYNC_I2S6 252 0725 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */ 0726 #define TEGRA186_CLK_SYNC_DSPK1 253 0727 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */ 0728 #define TEGRA186_CLK_SYNC_DSPK2 254 0729 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */ 0730 #define TEGRA186_CLK_SYNC_DMIC1 255 0731 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */ 0732 #define TEGRA186_CLK_SYNC_DMIC2 256 0733 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */ 0734 #define TEGRA186_CLK_SYNC_DMIC3 257 0735 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */ 0736 #define TEGRA186_CLK_SYNC_DMIC4 259 0737 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF */ 0738 #define TEGRA186_CLK_SYNC_SPDIF 260 0739 /** @brief output of gate CLK_ENB_PLLREFE_OUT */ 0740 #define TEGRA186_CLK_PLLREFE_OUT_GATED 261 0741 /** @brief output of the divider PLLREFE_DIVP in CLK_RST_CONTROLLER_PLLREFE_BASE. PLLREFE has 2 outputs: 0742 * * VCO/pdiv defined by this clock object 0743 * * VCO/2 defined by TEGRA186_CLK_PLLREFE_OUT 0744 */ 0745 #define TEGRA186_CLK_PLLREFE_OUT1 262 0746 #define TEGRA186_CLK_PLLD_OUT1 267 0747 /** @brief output of the divider PLLP_DIVP in CLK_RST_CONTROLLER_PLLP_BASE */ 0748 #define TEGRA186_CLK_PLLP_OUT0 269 0749 /** @brief output of the divider CLK_RST_CONTROLLER_PLLP_OUTC */ 0750 #define TEGRA186_CLK_PLLP_OUT5 270 0751 /** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */ 0752 #define TEGRA186_CLK_PLLA 271 0753 /** @brief output of mux controlled by CLK_RST_CONTROLLER_ACLK_BURST_POLICY divided by the divider controlled by ACLK_CLK_DIVISOR in CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER */ 0754 #define TEGRA186_CLK_ACLK 273 0755 /** fixed 48MHz clock divided down from TEGRA186_CLK_PLL_U */ 0756 #define TEGRA186_CLK_PLL_U_48M 274 0757 /** fixed 480MHz clock divided down from TEGRA186_CLK_PLL_U */ 0758 #define TEGRA186_CLK_PLL_U_480M 275 0759 /** @brief output of the divider PLLC4_DIVP in CLK_RST_CONTROLLER_PLLC4_BASE. Output frequency is TEGRA186_CLK_PLLC4_VCO/PLLC4_DIVP */ 0760 #define TEGRA186_CLK_PLLC4_OUT0 276 0761 /** fixed /3 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/3 */ 0762 #define TEGRA186_CLK_PLLC4_OUT1 277 0763 /** fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/5 */ 0764 #define TEGRA186_CLK_PLLC4_OUT2 278 0765 /** @brief output of mux controlled by PLLC4_CLK_SEL in CLK_RST_CONTROLLER_PLLC4_MISC1 */ 0766 #define TEGRA186_CLK_PLLC4_OUT_MUX 279 0767 /** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when DFLLDISP_DIV is selected in NVDISPLAY_DISP_CLK_SRC */ 0768 #define TEGRA186_CLK_DFLLDISP_DIV 284 0769 /** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when PLLDISPHUB_DIV is selected in NVDISPLAY_DISP_CLK_SRC */ 0770 #define TEGRA186_CLK_PLLDISPHUB_DIV 285 0771 /** fixed /8 divider which is used as the input for TEGRA186_CLK_SOR_SAFE */ 0772 #define TEGRA186_CLK_PLLP_DIV8 286 0773 /** @brief output of divider CLK_RST_CONTROLLER_BPMP_NIC_RATE */ 0774 #define TEGRA186_CLK_BPMP_NIC 287 0775 /** @brief output of the divider CLK_RST_CONTROLLER_PLLA1_OUT1 */ 0776 #define TEGRA186_CLK_PLL_A_OUT1 288 0777 /** @deprecated */ 0778 #define TEGRA186_CLK_GPC2CLK 289 0779 /** A fake clock which must be enabled during KFUSE read operations to ensure adequate VDD_CORE voltage. */ 0780 #define TEGRA186_CLK_KFUSE 293 0781 /** 0782 * @brief controls the PLLE hardware sequencer. 0783 * @details This clock only has enable and disable methods. When the 0784 * PLLE hw sequencer is enabled, PLLE, will be enabled or disabled by 0785 * hw based on the control signals from the PCIe, SATA and XUSB 0786 * clocks. When the PLLE hw sequencer is disabled, the state of PLLE 0787 * is controlled by sw using clk_enable/clk_disable on 0788 * TEGRA186_CLK_PLLE. 0789 */ 0790 #define TEGRA186_CLK_PLLE_PWRSEQ 294 0791 /** fixed 60MHz clock divided down from, TEGRA186_CLK_PLL_U */ 0792 #define TEGRA186_CLK_PLLREFE_REF 295 0793 /** @brief output of mux controlled by SOR0_CLK_SEL0 and SOR0_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */ 0794 #define TEGRA186_CLK_SOR0_OUT 296 0795 /** @brief output of mux controlled by SOR1_CLK_SEL0 and SOR1_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */ 0796 #define TEGRA186_CLK_SOR1_OUT 297 0797 /** @brief fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLREFE_OUT1/5. Used as input for TEGRA186_CLK_EQOS_AXI */ 0798 #define TEGRA186_CLK_PLLREFE_OUT1_DIV5 298 0799 /** @brief controls the UTMIP_PLL (aka PLLU) hardware sqeuencer */ 0800 #define TEGRA186_CLK_UTMIP_PLL_PWRSEQ 301 0801 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT */ 0802 #define TEGRA186_CLK_PEX_USB_PAD0_MGMT 302 0803 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT */ 0804 #define TEGRA186_CLK_PEX_USB_PAD1_MGMT 303 0805 /** @brief controls the UPHY_PLL0 hardware sqeuencer */ 0806 #define TEGRA186_CLK_UPHY_PLL0_PWRSEQ 304 0807 /** @brief controls the UPHY_PLL1 hardware sqeuencer */ 0808 #define TEGRA186_CLK_UPHY_PLL1_PWRSEQ 305 0809 /** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC so the bypass output even be used when the PLL is disabled */ 0810 #define TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH 306 0811 /** @brief output of the mux controlled by PLLREFE_SEL_CLKIN_PEX in CLK_RST_CONTROLLER_PLLREFE_MISC */ 0812 #define TEGRA186_CLK_PLLREFE_PEX 307 0813 /** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC to turn on the PLL when enabled */ 0814 #define TEGRA186_CLK_PLLREFE_IDDQ 308 0815 /** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */ 0816 #define TEGRA186_CLK_QSPI_OUT 309 0817 /** 0818 * @brief GPC2CLK-div-2 0819 * @details fixed /2 divider. Output frequency is 0820 * TEGRA186_CLK_GPC2CLK/2. The frequency of this clock is the 0821 * frequency at which the GPU graphics engine runs. */ 0822 #define TEGRA186_CLK_GPCCLK 310 0823 /** @brief output of divider CLK_RST_CONTROLLER_AON_NIC_RATE */ 0824 #define TEGRA186_CLK_AON_NIC 450 0825 /** @brief output of divider CLK_RST_CONTROLLER_SCE_NIC_RATE */ 0826 #define TEGRA186_CLK_SCE_NIC 451 0827 /** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */ 0828 #define TEGRA186_CLK_PLLE 512 0829 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC_BASE */ 0830 #define TEGRA186_CLK_PLLC 513 0831 /** Fixed 408MHz PLL for use by peripheral clocks */ 0832 #define TEGRA186_CLK_PLLP 516 0833 /** @deprecated */ 0834 #define TEGRA186_CLK_PLL_P TEGRA186_CLK_PLLP 0835 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD_BASE for use by DSI */ 0836 #define TEGRA186_CLK_PLLD 518 0837 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD2_BASE for use by HDMI or DP */ 0838 #define TEGRA186_CLK_PLLD2 519 0839 /** 0840 * @brief PLL controlled by CLK_RST_CONTROLLER_PLLREFE_BASE. 0841 * @details Note that this clock only controls the VCO output, before 0842 * the post-divider. See TEGRA186_CLK_PLLREFE_OUT1 for more 0843 * information. 0844 */ 0845 #define TEGRA186_CLK_PLLREFE_VCO 520 0846 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC2_BASE */ 0847 #define TEGRA186_CLK_PLLC2 521 0848 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC3_BASE */ 0849 #define TEGRA186_CLK_PLLC3 522 0850 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDP_BASE for use as the DP link clock */ 0851 #define TEGRA186_CLK_PLLDP 523 0852 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */ 0853 #define TEGRA186_CLK_PLLC4_VCO 524 0854 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLA1_BASE for use by audio clocks */ 0855 #define TEGRA186_CLK_PLLA1 525 0856 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVCSI_BASE */ 0857 #define TEGRA186_CLK_PLLNVCSI 526 0858 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDISPHUB_BASE */ 0859 #define TEGRA186_CLK_PLLDISPHUB 527 0860 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD3_BASE for use by HDMI or DP */ 0861 #define TEGRA186_CLK_PLLD3 528 0862 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLBPMPCAM_BASE */ 0863 #define TEGRA186_CLK_PLLBPMPCAM 531 0864 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLAON_BASE for use by IP blocks in the AON domain */ 0865 #define TEGRA186_CLK_PLLAON 532 0866 /** Fixed frequency 960MHz PLL for USB and EAVB */ 0867 #define TEGRA186_CLK_PLLU 533 0868 /** fixed /2 divider. Output frequency is TEGRA186_CLK_PLLC4_VCO/2 */ 0869 #define TEGRA186_CLK_PLLC4_VCO_DIV2 535 0870 /** @brief NAFLL clock source for AXI_CBB */ 0871 #define TEGRA186_CLK_NAFLL_AXI_CBB 564 0872 /** @brief NAFLL clock source for BPMP */ 0873 #define TEGRA186_CLK_NAFLL_BPMP 565 0874 /** @brief NAFLL clock source for ISP */ 0875 #define TEGRA186_CLK_NAFLL_ISP 566 0876 /** @brief NAFLL clock source for NVDEC */ 0877 #define TEGRA186_CLK_NAFLL_NVDEC 567 0878 /** @brief NAFLL clock source for NVENC */ 0879 #define TEGRA186_CLK_NAFLL_NVENC 568 0880 /** @brief NAFLL clock source for NVJPG */ 0881 #define TEGRA186_CLK_NAFLL_NVJPG 569 0882 /** @brief NAFLL clock source for SCE */ 0883 #define TEGRA186_CLK_NAFLL_SCE 570 0884 /** @brief NAFLL clock source for SE */ 0885 #define TEGRA186_CLK_NAFLL_SE 571 0886 /** @brief NAFLL clock source for TSEC */ 0887 #define TEGRA186_CLK_NAFLL_TSEC 572 0888 /** @brief NAFLL clock source for TSECB */ 0889 #define TEGRA186_CLK_NAFLL_TSECB 573 0890 /** @brief NAFLL clock source for VI */ 0891 #define TEGRA186_CLK_NAFLL_VI 574 0892 /** @brief NAFLL clock source for VIC */ 0893 #define TEGRA186_CLK_NAFLL_VIC 575 0894 /** @brief NAFLL clock source for DISP */ 0895 #define TEGRA186_CLK_NAFLL_DISP 576 0896 /** @brief NAFLL clock source for GPU */ 0897 #define TEGRA186_CLK_NAFLL_GPU 577 0898 /** @brief NAFLL clock source for M-CPU cluster */ 0899 #define TEGRA186_CLK_NAFLL_MCPU 578 0900 /** @brief NAFLL clock source for B-CPU cluster */ 0901 #define TEGRA186_CLK_NAFLL_BCPU 579 0902 /** @brief input from Tegra's CLK_32K_IN pad */ 0903 #define TEGRA186_CLK_CLK_32K 608 0904 /** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */ 0905 #define TEGRA186_CLK_CLK_M 609 0906 /** @brief output of divider PLL_REF_DIV in CLK_RST_CONTROLLER_OSC_CTRL */ 0907 #define TEGRA186_CLK_PLL_REF 610 0908 /** @brief input from Tegra's XTAL_IN */ 0909 #define TEGRA186_CLK_OSC 612 0910 /** @brief clock recovered from EAVB input */ 0911 #define TEGRA186_CLK_EQOS_RX_INPUT 613 0912 /** @brief clock recovered from DTV input */ 0913 #define TEGRA186_CLK_DTV_INPUT 614 0914 /** @brief SOR0 brick output which feeds into SOR0_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0*/ 0915 #define TEGRA186_CLK_SOR0_PAD_CLKOUT 615 0916 /** @brief SOR1 brick output which feeds into SOR1_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1*/ 0917 #define TEGRA186_CLK_SOR1_PAD_CLKOUT 616 0918 /** @brief clock recovered from I2S1 input */ 0919 #define TEGRA186_CLK_I2S1_SYNC_INPUT 617 0920 /** @brief clock recovered from I2S2 input */ 0921 #define TEGRA186_CLK_I2S2_SYNC_INPUT 618 0922 /** @brief clock recovered from I2S3 input */ 0923 #define TEGRA186_CLK_I2S3_SYNC_INPUT 619 0924 /** @brief clock recovered from I2S4 input */ 0925 #define TEGRA186_CLK_I2S4_SYNC_INPUT 620 0926 /** @brief clock recovered from I2S5 input */ 0927 #define TEGRA186_CLK_I2S5_SYNC_INPUT 621 0928 /** @brief clock recovered from I2S6 input */ 0929 #define TEGRA186_CLK_I2S6_SYNC_INPUT 622 0930 /** @brief clock recovered from SPDIFIN input */ 0931 #define TEGRA186_CLK_SPDIFIN_SYNC_INPUT 623 0932 0933 /** 0934 * @brief subject to change 0935 * @details maximum clock identifier value plus one. 0936 */ 0937 #define TEGRA186_CLK_CLK_MAX 624 0938 0939 /** @} */ 0940 0941 #endif
| [ Source navigation ] | [ Diff markup ] | [ Identifier search ] | [ general search ] |
|
This page was automatically generated by the 2.1.0 LXR engine. The LXR team |
|