dt-bindings/clock/tegra114-car.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * This header provides constants for binding nvidia,tegra114-car.
0004  *
0005  * The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
0006  * registers. These IDs often match those in the CAR's RST_DEVICES registers,
0007  * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
0008  * this case, those clocks are assigned IDs above 160 in order to highlight
0009  * this issue. Implementations that interpret these clock IDs as bit values
0010  * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
0011  * explicitly handle these special cases.
0012  *
0013  * The balance of the clocks controlled by the CAR are assigned IDs of 160 and
0014  * above.
0015  */
0016
0017 #ifndef _DT_BINDINGS_CLOCK_TEGRA114_CAR_H
0018 #define _DT_BINDINGS_CLOCK_TEGRA114_CAR_H
0019
0020 /* 0 */
0021 /* 1 */
0022 /* 2 */
0023 /* 3 */
0024 #define TEGRA114_CLK_RTC 4
0025 #define TEGRA114_CLK_TIMER 5
0026 #define TEGRA114_CLK_UARTA 6
0027 /* 7 (register bit affects uartb and vfir) */
0028 /* 8 */
0029 #define TEGRA114_CLK_SDMMC2 9
0030 /* 10 (register bit affects spdif_in and spdif_out) */
0031 #define TEGRA114_CLK_I2S1 11
0032 #define TEGRA114_CLK_I2C1 12
0033 #define TEGRA114_CLK_NDFLASH 13
0034 #define TEGRA114_CLK_SDMMC1 14
0035 #define TEGRA114_CLK_SDMMC4 15
0036 /* 16 */
0037 #define TEGRA114_CLK_PWM 17
0038 #define TEGRA114_CLK_I2S2 18
0039 #define TEGRA114_CLK_EPP 19
0040 /* 20 (register bit affects vi and vi_sensor) */
0041 #define TEGRA114_CLK_GR2D 21
0042 #define TEGRA114_CLK_USBD 22
0043 #define TEGRA114_CLK_ISP 23
0044 #define TEGRA114_CLK_GR3D 24
0045 /* 25 */
0046 #define TEGRA114_CLK_DISP2 26
0047 #define TEGRA114_CLK_DISP1 27
0048 #define TEGRA114_CLK_HOST1X 28
0049 #define TEGRA114_CLK_VCP 29
0050 #define TEGRA114_CLK_I2S0 30
0051 /* 31 */
0052
0053 #define TEGRA114_CLK_MC 32
0054 /* 33 */
0055 #define TEGRA114_CLK_APBDMA 34
0056 /* 35 */
0057 #define TEGRA114_CLK_KBC 36
0058 /* 37 */
0059 /* 38 */
0060 /* 39 (register bit affects fuse and fuse_burn) */
0061 #define TEGRA114_CLK_KFUSE 40
0062 #define TEGRA114_CLK_SBC1 41
0063 #define TEGRA114_CLK_NOR 42
0064 /* 43 */
0065 #define TEGRA114_CLK_SBC2 44
0066 /* 45 */
0067 #define TEGRA114_CLK_SBC3 46
0068 #define TEGRA114_CLK_I2C5 47
0069 #define TEGRA114_CLK_DSIA 48
0070 /* 49 */
0071 #define TEGRA114_CLK_MIPI 50
0072 #define TEGRA114_CLK_HDMI 51
0073 #define TEGRA114_CLK_CSI 52
0074 /* 53 */
0075 #define TEGRA114_CLK_I2C2 54
0076 #define TEGRA114_CLK_UARTC 55
0077 #define TEGRA114_CLK_MIPI_CAL 56
0078 #define TEGRA114_CLK_EMC 57
0079 #define TEGRA114_CLK_USB2 58
0080 #define TEGRA114_CLK_USB3 59
0081 /* 60 */
0082 #define TEGRA114_CLK_VDE 61
0083 #define TEGRA114_CLK_BSEA 62
0084 #define TEGRA114_CLK_BSEV 63
0085
0086 /* 64 */
0087 #define TEGRA114_CLK_UARTD 65
0088 /* 66 */
0089 #define TEGRA114_CLK_I2C3 67
0090 #define TEGRA114_CLK_SBC4 68
0091 #define TEGRA114_CLK_SDMMC3 69
0092 /* 70 */
0093 #define TEGRA114_CLK_OWR 71
0094 /* 72 */
0095 #define TEGRA114_CLK_CSITE 73
0096 /* 74 */
0097 /* 75 */
0098 #define TEGRA114_CLK_LA 76
0099 #define TEGRA114_CLK_TRACE 77
0100 #define TEGRA114_CLK_SOC_THERM 78
0101 #define TEGRA114_CLK_DTV 79
0102 #define TEGRA114_CLK_NDSPEED 80
0103 #define TEGRA114_CLK_I2CSLOW 81
0104 #define TEGRA114_CLK_DSIB 82
0105 #define TEGRA114_CLK_TSEC 83
0106 /* 84 */
0107 /* 85 */
0108 /* 86 */
0109 /* 87 */
0110 /* 88 */
0111 #define TEGRA114_CLK_XUSB_HOST 89
0112 /* 90 */
0113 #define TEGRA114_CLK_MSENC 91
0114 #define TEGRA114_CLK_CSUS 92
0115 /* 93 */
0116 /* 94 */
0117 /* 95 (bit affects xusb_dev and xusb_dev_src) */
0118
0119 /* 96 */
0120 /* 97 */
0121 /* 98 */
0122 #define TEGRA114_CLK_MSELECT 99
0123 #define TEGRA114_CLK_TSENSOR 100
0124 #define TEGRA114_CLK_I2S3 101
0125 #define TEGRA114_CLK_I2S4 102
0126 #define TEGRA114_CLK_I2C4 103
0127 #define TEGRA114_CLK_SBC5 104
0128 #define TEGRA114_CLK_SBC6 105
0129 #define TEGRA114_CLK_D_AUDIO 106
0130 #define TEGRA114_CLK_APBIF 107
0131 #define TEGRA114_CLK_DAM0 108
0132 #define TEGRA114_CLK_DAM1 109
0133 #define TEGRA114_CLK_DAM2 110
0134 #define TEGRA114_CLK_HDA2CODEC_2X 111
0135 /* 112 */
0136 #define TEGRA114_CLK_AUDIO0_2X 113
0137 #define TEGRA114_CLK_AUDIO1_2X 114
0138 #define TEGRA114_CLK_AUDIO2_2X 115
0139 #define TEGRA114_CLK_AUDIO3_2X 116
0140 #define TEGRA114_CLK_AUDIO4_2X 117
0141 #define TEGRA114_CLK_SPDIF_2X 118
0142 #define TEGRA114_CLK_ACTMON 119
0143 #define TEGRA114_CLK_EXTERN1 120
0144 #define TEGRA114_CLK_EXTERN2 121
0145 #define TEGRA114_CLK_EXTERN3 122
0146 /* 123 */
0147 /* 124 */
0148 #define TEGRA114_CLK_HDA 125
0149 /* 126 */
0150 #define TEGRA114_CLK_SE 127
0151
0152 #define TEGRA114_CLK_HDA2HDMI 128
0153 /* 129 */
0154 /* 130 */
0155 /* 131 */
0156 /* 132 */
0157 /* 133 */
0158 /* 134 */
0159 /* 135 */
0160 #define TEGRA114_CLK_CEC 136
0161 /* 137 */
0162 /* 138 */
0163 /* 139 */
0164 /* 140 */
0165 /* 141 */
0166 /* 142 */
0167 /* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
0168 /*      xusb_host_src and xusb_ss_src) */
0169 #define TEGRA114_CLK_CILAB 144
0170 #define TEGRA114_CLK_CILCD 145
0171 #define TEGRA114_CLK_CILE 146
0172 #define TEGRA114_CLK_DSIALP 147
0173 #define TEGRA114_CLK_DSIBLP 148
0174 /* 149 */
0175 #define TEGRA114_CLK_DDS 150
0176 /* 151 */
0177 #define TEGRA114_CLK_DP2 152
0178 #define TEGRA114_CLK_AMX 153
0179 #define TEGRA114_CLK_ADX 154
0180 /* 155 (bit affects dfll_ref and dfll_soc) */
0181 #define TEGRA114_CLK_XUSB_SS 156
0182 /* 157 */
0183 /* 158 */
0184 /* 159 */
0185
0186 /* 160 */
0187 /* 161 */
0188 /* 162 */
0189 /* 163 */
0190 /* 164 */
0191 /* 165 */
0192 /* 166 */
0193 /* 167 */
0194 /* 168 */
0195 /* 169 */
0196 /* 170 */
0197 /* 171 */
0198 /* 172 */
0199 /* 173 */
0200 /* 174 */
0201 /* 175 */
0202 /* 176 */
0203 /* 177 */
0204 /* 178 */
0205 /* 179 */
0206 /* 180 */
0207 /* 181 */
0208 /* 182 */
0209 /* 183 */
0210 /* 184 */
0211 /* 185 */
0212 /* 186 */
0213 /* 187 */
0214 /* 188 */
0215 /* 189 */
0216 /* 190 */
0217 /* 191 */
0218
0219 #define TEGRA114_CLK_UARTB 192
0220 #define TEGRA114_CLK_VFIR 193
0221 #define TEGRA114_CLK_SPDIF_IN 194
0222 #define TEGRA114_CLK_SPDIF_OUT 195
0223 #define TEGRA114_CLK_VI 196
0224 #define TEGRA114_CLK_VI_SENSOR 197
0225 #define TEGRA114_CLK_FUSE 198
0226 #define TEGRA114_CLK_FUSE_BURN 199
0227 #define TEGRA114_CLK_CLK_32K 200
0228 #define TEGRA114_CLK_CLK_M 201
0229 #define TEGRA114_CLK_CLK_M_DIV2 202
0230 #define TEGRA114_CLK_CLK_M_DIV4 203
0231 #define TEGRA114_CLK_OSC_DIV2 202
0232 #define TEGRA114_CLK_OSC_DIV4 203
0233 #define TEGRA114_CLK_PLL_REF 204
0234 #define TEGRA114_CLK_PLL_C 205
0235 #define TEGRA114_CLK_PLL_C_OUT1 206
0236 #define TEGRA114_CLK_PLL_C2 207
0237 #define TEGRA114_CLK_PLL_C3 208
0238 #define TEGRA114_CLK_PLL_M 209
0239 #define TEGRA114_CLK_PLL_M_OUT1 210
0240 #define TEGRA114_CLK_PLL_P 211
0241 #define TEGRA114_CLK_PLL_P_OUT1 212
0242 #define TEGRA114_CLK_PLL_P_OUT2 213
0243 #define TEGRA114_CLK_PLL_P_OUT3 214
0244 #define TEGRA114_CLK_PLL_P_OUT4 215
0245 #define TEGRA114_CLK_PLL_A 216
0246 #define TEGRA114_CLK_PLL_A_OUT0 217
0247 #define TEGRA114_CLK_PLL_D 218
0248 #define TEGRA114_CLK_PLL_D_OUT0 219
0249 #define TEGRA114_CLK_PLL_D2 220
0250 #define TEGRA114_CLK_PLL_D2_OUT0 221
0251 #define TEGRA114_CLK_PLL_U 222
0252 #define TEGRA114_CLK_PLL_U_480M 223
0253
0254 #define TEGRA114_CLK_PLL_U_60M 224
0255 #define TEGRA114_CLK_PLL_U_48M 225
0256 #define TEGRA114_CLK_PLL_U_12M 226
0257 #define TEGRA114_CLK_PLL_X 227
0258 #define TEGRA114_CLK_PLL_X_OUT0 228
0259 #define TEGRA114_CLK_PLL_RE_VCO 229
0260 #define TEGRA114_CLK_PLL_RE_OUT 230
0261 #define TEGRA114_CLK_PLL_E_OUT0 231
0262 #define TEGRA114_CLK_SPDIF_IN_SYNC 232
0263 #define TEGRA114_CLK_I2S0_SYNC 233
0264 #define TEGRA114_CLK_I2S1_SYNC 234
0265 #define TEGRA114_CLK_I2S2_SYNC 235
0266 #define TEGRA114_CLK_I2S3_SYNC 236
0267 #define TEGRA114_CLK_I2S4_SYNC 237
0268 #define TEGRA114_CLK_VIMCLK_SYNC 238
0269 #define TEGRA114_CLK_AUDIO0 239
0270 #define TEGRA114_CLK_AUDIO1 240
0271 #define TEGRA114_CLK_AUDIO2 241
0272 #define TEGRA114_CLK_AUDIO3 242
0273 #define TEGRA114_CLK_AUDIO4 243
0274 #define TEGRA114_CLK_SPDIF 244
0275 /* 245 */
0276 /* 246 */
0277 /* 247 */
0278 /* 248 */
0279 #define TEGRA114_CLK_OSC 249
0280 /* 250 */
0281 /* 251 */
0282 #define TEGRA114_CLK_XUSB_HOST_SRC 252
0283 #define TEGRA114_CLK_XUSB_FALCON_SRC 253
0284 #define TEGRA114_CLK_XUSB_FS_SRC 254
0285 #define TEGRA114_CLK_XUSB_SS_SRC 255
0286
0287 #define TEGRA114_CLK_XUSB_DEV_SRC 256
0288 #define TEGRA114_CLK_XUSB_DEV 257
0289 #define TEGRA114_CLK_XUSB_HS_SRC 258
0290 #define TEGRA114_CLK_SCLK 259
0291 #define TEGRA114_CLK_HCLK 260
0292 #define TEGRA114_CLK_PCLK 261
0293 #define TEGRA114_CLK_CCLK_G 262
0294 #define TEGRA114_CLK_CCLK_LP 263
0295 #define TEGRA114_CLK_DFLL_REF 264
0296 #define TEGRA114_CLK_DFLL_SOC 265
0297 /* 266 */
0298 /* 267 */
0299 /* 268 */
0300 /* 269 */
0301 /* 270 */
0302 /* 271 */
0303 /* 272 */
0304 /* 273 */
0305 /* 274 */
0306 /* 275 */
0307 /* 276 */
0308 /* 277 */
0309 /* 278 */
0310 /* 279 */
0311 /* 280 */
0312 /* 281 */
0313 /* 282 */
0314 /* 283 */
0315 /* 284 */
0316 /* 285 */
0317 /* 286 */
0318 /* 287 */
0319
0320 /* 288 */
0321 /* 289 */
0322 /* 290 */
0323 /* 291 */
0324 /* 292 */
0325 /* 293 */
0326 /* 294 */
0327 /* 295 */
0328 /* 296 */
0329 /* 297 */
0330 /* 298 */
0331 /* 299 */
0332 #define TEGRA114_CLK_AUDIO0_MUX 300
0333 #define TEGRA114_CLK_AUDIO1_MUX 301
0334 #define TEGRA114_CLK_AUDIO2_MUX 302
0335 #define TEGRA114_CLK_AUDIO3_MUX 303
0336 #define TEGRA114_CLK_AUDIO4_MUX 304
0337 #define TEGRA114_CLK_SPDIF_MUX 305
0338 /* 306 */
0339 /* 307 */
0340 /* 308 */
0341 #define TEGRA114_CLK_DSIA_MUX 309
0342 #define TEGRA114_CLK_DSIB_MUX 310
0343 #define TEGRA114_CLK_XUSB_SS_DIV2 311
0344 #define TEGRA114_CLK_CLK_MAX 312
0345
0346 #endif  /* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */