dt-bindings/clock/sunplus%2Csp7021-clkc.h

0001 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
0002 /*
0003  * Copyright (C) Sunplus Technology Co., Ltd.
0004  *       All rights reserved.
0005  */
0006 #ifndef _DT_BINDINGS_CLOCK_SUNPLUS_SP7021_H
0007 #define _DT_BINDINGS_CLOCK_SUNPLUS_SP7021_H
0008
0009 /* gates */
0010 #define CLK_RTC         0
0011 #define CLK_OTPRX       1
0012 #define CLK_NOC         2
0013 #define CLK_BR          3
0014 #define CLK_SPIFL       4
0015 #define CLK_PERI0       5
0016 #define CLK_PERI1       6
0017 #define CLK_STC0        7
0018 #define CLK_STC_AV0     8
0019 #define CLK_STC_AV1     9
0020 #define CLK_STC_AV2     10
0021 #define CLK_UA0         11
0022 #define CLK_UA1         12
0023 #define CLK_UA2         13
0024 #define CLK_UA3         14
0025 #define CLK_UA4         15
0026 #define CLK_HWUA        16
0027 #define CLK_DDC0        17
0028 #define CLK_UADMA       18
0029 #define CLK_CBDMA0      19
0030 #define CLK_CBDMA1      20
0031 #define CLK_SPI_COMBO_0 21
0032 #define CLK_SPI_COMBO_1 22
0033 #define CLK_SPI_COMBO_2 23
0034 #define CLK_SPI_COMBO_3 24
0035 #define CLK_AUD         25
0036 #define CLK_USBC0       26
0037 #define CLK_USBC1       27
0038 #define CLK_UPHY0       28
0039 #define CLK_UPHY1       29
0040 #define CLK_I2CM0       30
0041 #define CLK_I2CM1       31
0042 #define CLK_I2CM2       32
0043 #define CLK_I2CM3       33
0044 #define CLK_PMC         34
0045 #define CLK_CARD_CTL0   35
0046 #define CLK_CARD_CTL1   36
0047 #define CLK_CARD_CTL4   37
0048 #define CLK_BCH         38
0049 #define CLK_DDFCH       39
0050 #define CLK_CSIIW0      40
0051 #define CLK_CSIIW1      41
0052 #define CLK_MIPICSI0    42
0053 #define CLK_MIPICSI1    43
0054 #define CLK_HDMI_TX     44
0055 #define CLK_VPOST       45
0056 #define CLK_TGEN        46
0057 #define CLK_DMIX        47
0058 #define CLK_TCON        48
0059 #define CLK_GPIO        49
0060 #define CLK_MAILBOX     50
0061 #define CLK_SPIND       51
0062 #define CLK_I2C2CBUS    52
0063 #define CLK_SEC         53
0064 #define CLK_DVE         54
0065 #define CLK_GPOST0      55
0066 #define CLK_OSD0        56
0067 #define CLK_DISP_PWM    57
0068 #define CLK_UADBG       58
0069 #define CLK_FIO_CTL     59
0070 #define CLK_FPGA        60
0071 #define CLK_L2SW        61
0072 #define CLK_ICM         62
0073 #define CLK_AXI_GLOBAL  63
0074
0075 /* plls */
0076 #define PLL_A           64
0077 #define PLL_E           65
0078 #define PLL_E_2P5       66
0079 #define PLL_E_25        67
0080 #define PLL_E_112P5     68
0081 #define PLL_F           69
0082 #define PLL_TV          70
0083 #define PLL_TV_A        71
0084 #define PLL_SYS         72
0085
0086 #define CLK_MAX         73
0087
0088 #endif