0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011
0012
0013
0014
0015
0016
0017
0018
0019
0020
0021
0022
0023
0024
0025
0026
0027
0028
0029
0030
0031
0032
0033
0034
0035
0036
0037
0038
0039
0040
0041
0042
0043 #ifndef _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_
0044 #define _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_
0045
0046 #define CLK_PLL_PERIPH 6
0047
0048 #define CLK_PLL_DE 9
0049
0050 #define CLK_C0CPUX 11
0051 #define CLK_C1CPUX 12
0052
0053 #define CLK_BUS_MIPI_DSI 19
0054 #define CLK_BUS_SS 20
0055 #define CLK_BUS_DMA 21
0056 #define CLK_BUS_MMC0 22
0057 #define CLK_BUS_MMC1 23
0058 #define CLK_BUS_MMC2 24
0059 #define CLK_BUS_NAND 25
0060 #define CLK_BUS_DRAM 26
0061 #define CLK_BUS_EMAC 27
0062 #define CLK_BUS_HSTIMER 28
0063 #define CLK_BUS_SPI0 29
0064 #define CLK_BUS_SPI1 30
0065 #define CLK_BUS_OTG 31
0066 #define CLK_BUS_EHCI0 32
0067 #define CLK_BUS_EHCI1 33
0068 #define CLK_BUS_OHCI0 34
0069
0070 #define CLK_BUS_VE 35
0071 #define CLK_BUS_TCON0 36
0072 #define CLK_BUS_TCON1 37
0073 #define CLK_BUS_CSI 38
0074 #define CLK_BUS_HDMI 39
0075 #define CLK_BUS_DE 40
0076 #define CLK_BUS_GPU 41
0077 #define CLK_BUS_MSGBOX 42
0078 #define CLK_BUS_SPINLOCK 43
0079
0080 #define CLK_BUS_SPDIF 44
0081 #define CLK_BUS_PIO 45
0082 #define CLK_BUS_I2S0 46
0083 #define CLK_BUS_I2S1 47
0084 #define CLK_BUS_I2S2 48
0085 #define CLK_BUS_TDM 49
0086
0087 #define CLK_BUS_I2C0 50
0088 #define CLK_BUS_I2C1 51
0089 #define CLK_BUS_I2C2 52
0090 #define CLK_BUS_UART0 53
0091 #define CLK_BUS_UART1 54
0092 #define CLK_BUS_UART2 55
0093 #define CLK_BUS_UART3 56
0094 #define CLK_BUS_UART4 57
0095
0096 #define CLK_NAND 59
0097 #define CLK_MMC0 60
0098 #define CLK_MMC0_SAMPLE 61
0099 #define CLK_MMC0_OUTPUT 62
0100 #define CLK_MMC1 63
0101 #define CLK_MMC1_SAMPLE 64
0102 #define CLK_MMC1_OUTPUT 65
0103 #define CLK_MMC2 66
0104 #define CLK_MMC2_SAMPLE 67
0105 #define CLK_MMC2_OUTPUT 68
0106 #define CLK_SS 69
0107 #define CLK_SPI0 70
0108 #define CLK_SPI1 71
0109 #define CLK_I2S0 72
0110 #define CLK_I2S1 73
0111 #define CLK_I2S2 74
0112 #define CLK_TDM 75
0113 #define CLK_SPDIF 76
0114 #define CLK_USB_PHY0 77
0115 #define CLK_USB_PHY1 78
0116 #define CLK_USB_HSIC 79
0117 #define CLK_USB_HSIC_12M 80
0118 #define CLK_USB_OHCI0 81
0119
0120 #define CLK_DRAM_VE 83
0121 #define CLK_DRAM_CSI 84
0122
0123 #define CLK_TCON0 85
0124 #define CLK_TCON1 86
0125 #define CLK_CSI_MISC 87
0126 #define CLK_MIPI_CSI 88
0127 #define CLK_CSI_MCLK 89
0128 #define CLK_CSI_SCLK 90
0129 #define CLK_VE 91
0130 #define CLK_AVS 92
0131 #define CLK_HDMI 93
0132 #define CLK_HDMI_SLOW 94
0133
0134 #define CLK_MIPI_DSI0 96
0135 #define CLK_MIPI_DSI1 97
0136 #define CLK_GPU_CORE 98
0137 #define CLK_GPU_MEMORY 99
0138 #define CLK_GPU_HYD 100
0139
0140 #endif