dt-bindings/clock/sun50i-a100-ccu.h

0001 /* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
0002 /*
0003  * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
0004  */
0005
0006 #ifndef _DT_BINDINGS_CLK_SUN50I_A100_H_
0007 #define _DT_BINDINGS_CLK_SUN50I_A100_H_
0008
0009 #define CLK_PLL_PERIPH0     3
0010
0011 #define CLK_CPUX        24
0012
0013 #define CLK_APB1        29
0014
0015 #define CLK_MBUS        31
0016 #define CLK_DE          32
0017 #define CLK_BUS_DE      33
0018 #define CLK_G2D         34
0019 #define CLK_BUS_G2D     35
0020 #define CLK_GPU         36
0021 #define CLK_BUS_GPU     37
0022 #define CLK_CE          38
0023 #define CLK_BUS_CE      39
0024 #define CLK_VE          40
0025 #define CLK_BUS_VE      41
0026 #define CLK_BUS_DMA     42
0027 #define CLK_BUS_MSGBOX      43
0028 #define CLK_BUS_SPINLOCK    44
0029 #define CLK_BUS_HSTIMER     45
0030 #define CLK_AVS         46
0031 #define CLK_BUS_DBG     47
0032 #define CLK_BUS_PSI     48
0033 #define CLK_BUS_PWM     49
0034 #define CLK_BUS_IOMMU       50
0035 #define CLK_MBUS_DMA        51
0036 #define CLK_MBUS_VE     52
0037 #define CLK_MBUS_CE     53
0038 #define CLK_MBUS_NAND       54
0039 #define CLK_MBUS_CSI        55
0040 #define CLK_MBUS_ISP        56
0041 #define CLK_MBUS_G2D        57
0042
0043 #define CLK_NAND0       59
0044 #define CLK_NAND1       60
0045 #define CLK_BUS_NAND        61
0046 #define CLK_MMC0        62
0047 #define CLK_MMC1        63
0048 #define CLK_MMC2        64
0049 #define CLK_MMC3        65
0050 #define CLK_BUS_MMC0        66
0051 #define CLK_BUS_MMC1        67
0052 #define CLK_BUS_MMC2        68
0053 #define CLK_BUS_UART0       69
0054 #define CLK_BUS_UART1       70
0055 #define CLK_BUS_UART2       71
0056 #define CLK_BUS_UART3       72
0057 #define CLK_BUS_UART4       73
0058 #define CLK_BUS_I2C0        74
0059 #define CLK_BUS_I2C1        75
0060 #define CLK_BUS_I2C2        76
0061 #define CLK_BUS_I2C3        77
0062 #define CLK_SPI0        78
0063 #define CLK_SPI1        79
0064 #define CLK_SPI2        80
0065 #define CLK_BUS_SPI0        81
0066 #define CLK_BUS_SPI1        82
0067 #define CLK_BUS_SPI2        83
0068 #define CLK_EMAC_25M        84
0069 #define CLK_BUS_EMAC        85
0070 #define CLK_IR_RX       86
0071 #define CLK_BUS_IR_RX       87
0072 #define CLK_IR_TX       88
0073 #define CLK_BUS_IR_TX       89
0074 #define CLK_BUS_GPADC       90
0075 #define CLK_BUS_THS     91
0076 #define CLK_I2S0        92
0077 #define CLK_I2S1        93
0078 #define CLK_I2S2        94
0079 #define CLK_I2S3        95
0080 #define CLK_BUS_I2S0        96
0081 #define CLK_BUS_I2S1        97
0082 #define CLK_BUS_I2S2        98
0083 #define CLK_BUS_I2S3        99
0084 #define CLK_SPDIF       100
0085 #define CLK_BUS_SPDIF       101
0086 #define CLK_DMIC        102
0087 #define CLK_BUS_DMIC        103
0088 #define CLK_AUDIO_DAC       104
0089 #define CLK_AUDIO_ADC       105
0090 #define CLK_AUDIO_4X        106
0091 #define CLK_BUS_AUDIO_CODEC 107
0092 #define CLK_USB_OHCI0       108
0093 #define CLK_USB_PHY0        109
0094 #define CLK_USB_OHCI1       110
0095 #define CLK_USB_PHY1        111
0096 #define CLK_BUS_OHCI0       112
0097 #define CLK_BUS_OHCI1       113
0098 #define CLK_BUS_EHCI0       114
0099 #define CLK_BUS_EHCI1       115
0100 #define CLK_BUS_OTG     116
0101 #define CLK_BUS_LRADC       117
0102 #define CLK_BUS_DPSS_TOP0   118
0103 #define CLK_BUS_DPSS_TOP1   119
0104 #define CLK_MIPI_DSI        120
0105 #define CLK_BUS_MIPI_DSI    121
0106 #define CLK_TCON_LCD        122
0107 #define CLK_BUS_TCON_LCD    123
0108 #define CLK_LEDC        124
0109 #define CLK_BUS_LEDC        125
0110 #define CLK_CSI_TOP     126
0111 #define CLK_CSI0_MCLK       127
0112 #define CLK_CSI1_MCLK       128
0113 #define CLK_BUS_CSI     129
0114 #define CLK_CSI_ISP     130
0115
0116 #endif /* _DT_BINDINGS_CLK_SUN50I_A100_H_ */