0001
0002 #define SYS_D1CPRE 0
0003 #define HCLK 1
0004 #define PCLK1 2
0005 #define PCLK2 3
0006 #define PCLK3 4
0007 #define PCLK4 5
0008 #define HSI_DIV 6
0009 #define HSE_1M 7
0010 #define I2S_CKIN 8
0011 #define CK_DSI_PHY 9
0012 #define HSE_CK 10
0013 #define LSE_CK 11
0014 #define CSI_KER_DIV122 12
0015 #define RTC_CK 13
0016 #define CPU_SYSTICK 14
0017
0018
0019 #define OSC_BANK 18
0020 #define HSI_CK 18
0021 #define HSI_KER_CK 19
0022 #define CSI_CK 20
0023 #define CSI_KER_CK 21
0024 #define RC48_CK 22
0025 #define LSI_CK 23
0026
0027
0028 #define MCLK_BANK 28
0029 #define PER_CK 28
0030 #define PLLSRC 29
0031 #define SYS_CK 30
0032 #define TRACEIN_CK 31
0033
0034
0035 #define ODF_BANK 32
0036 #define PLL1_P 32
0037 #define PLL1_Q 33
0038 #define PLL1_R 34
0039 #define PLL2_P 35
0040 #define PLL2_Q 36
0041 #define PLL2_R 37
0042 #define PLL3_P 38
0043 #define PLL3_Q 39
0044 #define PLL3_R 40
0045
0046
0047 #define MCO_BANK 41
0048 #define MCO1 41
0049 #define MCO2 42
0050
0051
0052 #define PERIF_BANK 50
0053 #define D1SRAM1_CK 50
0054 #define ITCM_CK 51
0055 #define DTCM2_CK 52
0056 #define DTCM1_CK 53
0057 #define FLITF_CK 54
0058 #define JPGDEC_CK 55
0059 #define DMA2D_CK 56
0060 #define MDMA_CK 57
0061 #define USB2ULPI_CK 58
0062 #define USB1ULPI_CK 59
0063 #define ETH1RX_CK 60
0064 #define ETH1TX_CK 61
0065 #define ETH1MAC_CK 62
0066 #define ART_CK 63
0067 #define DMA2_CK 64
0068 #define DMA1_CK 65
0069 #define D2SRAM3_CK 66
0070 #define D2SRAM2_CK 67
0071 #define D2SRAM1_CK 68
0072 #define HASH_CK 69
0073 #define CRYPT_CK 70
0074 #define CAMITF_CK 71
0075 #define BKPRAM_CK 72
0076 #define HSEM_CK 73
0077 #define BDMA_CK 74
0078 #define CRC_CK 75
0079 #define GPIOK_CK 76
0080 #define GPIOJ_CK 77
0081 #define GPIOI_CK 78
0082 #define GPIOH_CK 79
0083 #define GPIOG_CK 80
0084 #define GPIOF_CK 81
0085 #define GPIOE_CK 82
0086 #define GPIOD_CK 83
0087 #define GPIOC_CK 84
0088 #define GPIOB_CK 85
0089 #define GPIOA_CK 86
0090 #define WWDG1_CK 87
0091 #define DAC12_CK 88
0092 #define WWDG2_CK 89
0093 #define TIM14_CK 90
0094 #define TIM13_CK 91
0095 #define TIM12_CK 92
0096 #define TIM7_CK 93
0097 #define TIM6_CK 94
0098 #define TIM5_CK 95
0099 #define TIM4_CK 96
0100 #define TIM3_CK 97
0101 #define TIM2_CK 98
0102 #define MDIOS_CK 99
0103 #define OPAMP_CK 100
0104 #define CRS_CK 101
0105 #define TIM17_CK 102
0106 #define TIM16_CK 103
0107 #define TIM15_CK 104
0108 #define TIM8_CK 105
0109 #define TIM1_CK 106
0110 #define TMPSENS_CK 107
0111 #define RTCAPB_CK 108
0112 #define VREF_CK 109
0113 #define COMP12_CK 110
0114 #define SYSCFG_CK 111
0115
0116
0117 #define KERN_BANK 120
0118 #define SDMMC1_CK 120
0119 #define QUADSPI_CK 121
0120 #define FMC_CK 122
0121 #define USB2OTG_CK 123
0122 #define USB1OTG_CK 124
0123 #define ADC12_CK 125
0124 #define SDMMC2_CK 126
0125 #define RNG_CK 127
0126 #define ADC3_CK 128
0127 #define DSI_CK 129
0128 #define LTDC_CK 130
0129 #define USART8_CK 131
0130 #define USART7_CK 132
0131 #define HDMICEC_CK 133
0132 #define I2C3_CK 134
0133 #define I2C2_CK 135
0134 #define I2C1_CK 136
0135 #define UART5_CK 137
0136 #define UART4_CK 138
0137 #define USART3_CK 139
0138 #define USART2_CK 140
0139 #define SPDIFRX_CK 141
0140 #define SPI3_CK 142
0141 #define SPI2_CK 143
0142 #define LPTIM1_CK 144
0143 #define FDCAN_CK 145
0144 #define SWP_CK 146
0145 #define HRTIM_CK 147
0146 #define DFSDM1_CK 148
0147 #define SAI3_CK 149
0148 #define SAI2_CK 150
0149 #define SAI1_CK 151
0150 #define SPI5_CK 152
0151 #define SPI4_CK 153
0152 #define SPI1_CK 154
0153 #define USART6_CK 155
0154 #define USART1_CK 156
0155 #define SAI4B_CK 157
0156 #define SAI4A_CK 158
0157 #define LPTIM5_CK 159
0158 #define LPTIM4_CK 160
0159 #define LPTIM3_CK 161
0160 #define LPTIM2_CK 162
0161 #define I2C4_CK 163
0162 #define SPI6_CK 164
0163 #define LPUART1_CK 165
0164
0165 #define STM32H7_MAX_CLKS 166