dt-bindings/clock/s3c2443.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
0004  *
0005  * Device Tree binding constants clock controllers of Samsung S3C2443 and later.
0006  */
0007
0008 #ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H
0009 #define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H
0010
0011 /*
0012  * Let each exported clock get a unique index, which is used on DT-enabled
0013  * platforms to lookup the clock from a clock specifier. These indices are
0014  * therefore considered an ABI and so must not be changed. This implies
0015  * that new clocks should be added either in free spaces between clock groups
0016  * or at the end.
0017  */
0018
0019 /* Core clocks. */
0020 #define MSYSCLK         1
0021 #define ESYSCLK         2
0022 #define ARMDIV          3
0023 #define ARMCLK          4
0024 #define HCLK            5
0025 #define PCLK            6
0026 #define MPLL            7
0027 #define EPLL            8
0028
0029 /* Special clocks */
0030 #define SCLK_HSSPI0     16
0031 #define SCLK_FIMD       17
0032 #define SCLK_I2S0       18
0033 #define SCLK_I2S1       19
0034 #define SCLK_HSMMC1     20
0035 #define SCLK_HSMMC_EXT      21
0036 #define SCLK_CAM        22
0037 #define SCLK_UART       23
0038 #define SCLK_USBH       24
0039
0040 /* Muxes */
0041 #define MUX_HSSPI0      32
0042 #define MUX_HSSPI1      33
0043 #define MUX_HSMMC0      34
0044 #define MUX_HSMMC1      35
0045
0046 /* hclk-gates */
0047 #define HCLK_DMA0       48
0048 #define HCLK_DMA1       49
0049 #define HCLK_DMA2       50
0050 #define HCLK_DMA3       51
0051 #define HCLK_DMA4       52
0052 #define HCLK_DMA5       53
0053 #define HCLK_DMA6       54
0054 #define HCLK_DMA7       55
0055 #define HCLK_CAM        56
0056 #define HCLK_LCD        57
0057 #define HCLK_USBH       58
0058 #define HCLK_USBD       59
0059 #define HCLK_IROM       60
0060 #define HCLK_HSMMC0     61
0061 #define HCLK_HSMMC1     62
0062 #define HCLK_CFC        63
0063 #define HCLK_SSMC       64
0064 #define HCLK_DRAM       65
0065 #define HCLK_2D         66
0066
0067 /* pclk-gates */
0068 #define PCLK_UART0      72
0069 #define PCLK_UART1      73
0070 #define PCLK_UART2      74
0071 #define PCLK_UART3      75
0072 #define PCLK_I2C0       76
0073 #define PCLK_SDI        77
0074 #define PCLK_SPI0       78
0075 #define PCLK_ADC        79
0076 #define PCLK_AC97       80
0077 #define PCLK_I2S0       81
0078 #define PCLK_PWM        82
0079 #define PCLK_WDT        83
0080 #define PCLK_RTC        84
0081 #define PCLK_GPIO       85
0082 #define PCLK_SPI1       86
0083 #define PCLK_CHIPID     87
0084 #define PCLK_I2C1       88
0085 #define PCLK_I2S1       89
0086 #define PCLK_PCM        90
0087
0088 /* Total number of clocks. */
0089 #define NR_CLKS         (PCLK_PCM + 1)
0090
0091 #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H */