dt-bindings/clock/s3c2410.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
0004  *
0005  * Device Tree binding constants clock controllers of Samsung S3C2410 and later.
0006  */
0007
0008 #ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2410_CLOCK_H
0009 #define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2410_CLOCK_H
0010
0011 /*
0012  * Let each exported clock get a unique index, which is used on DT-enabled
0013  * platforms to lookup the clock from a clock specifier. These indices are
0014  * therefore considered an ABI and so must not be changed. This implies
0015  * that new clocks should be added either in free spaces between clock groups
0016  * or at the end.
0017  */
0018
0019 /* Core clocks. */
0020
0021 /* id 1 is reserved */
0022 #define MPLL            2
0023 #define UPLL            3
0024 #define FCLK            4
0025 #define HCLK            5
0026 #define PCLK            6
0027 #define UCLK            7
0028 #define ARMCLK          8
0029
0030 /* pclk-gates */
0031 #define PCLK_UART0      16
0032 #define PCLK_UART1      17
0033 #define PCLK_UART2      18
0034 #define PCLK_I2C        19
0035 #define PCLK_SDI        20
0036 #define PCLK_SPI        21
0037 #define PCLK_ADC        22
0038 #define PCLK_AC97       23
0039 #define PCLK_I2S        24
0040 #define PCLK_PWM        25
0041 #define PCLK_RTC        26
0042 #define PCLK_GPIO       27
0043
0044
0045 /* hclk-gates */
0046 #define HCLK_LCD        32
0047 #define HCLK_USBH       33
0048 #define HCLK_USBD       34
0049 #define HCLK_NAND       35
0050 #define HCLK_CAM        36
0051
0052
0053 #define CAMIF           40
0054
0055
0056 /* Total number of clocks. */
0057 #define NR_CLKS         (CAMIF + 1)
0058
0059 #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H */