dt-bindings/clock/r9a07g043-cpg.h

0001 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002  *
0003  * Copyright (C) 2022 Renesas Electronics Corp.
0004  */
0005 #ifndef __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__
0006 #define __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__
0007
0008 #include <dt-bindings/clock/renesas-cpg-mssr.h>
0009
0010 /* R9A07G043 CPG Core Clocks */
0011 #define R9A07G043_CLK_I         0
0012 #define R9A07G043_CLK_I2        1
0013 #define R9A07G043_CLK_S0        2
0014 #define R9A07G043_CLK_SPI0      3
0015 #define R9A07G043_CLK_SPI1      4
0016 #define R9A07G043_CLK_SD0       5
0017 #define R9A07G043_CLK_SD1       6
0018 #define R9A07G043_CLK_M0        7
0019 #define R9A07G043_CLK_M2        8
0020 #define R9A07G043_CLK_M3        9
0021 #define R9A07G043_CLK_HP        10
0022 #define R9A07G043_CLK_TSU       11
0023 #define R9A07G043_CLK_ZT        12
0024 #define R9A07G043_CLK_P0        13
0025 #define R9A07G043_CLK_P1        14
0026 #define R9A07G043_CLK_P2        15
0027 #define R9A07G043_CLK_AT        16
0028 #define R9A07G043_OSCCLK        17
0029 #define R9A07G043_CLK_P0_DIV2       18
0030
0031 /* R9A07G043 Module Clocks */
0032 #define R9A07G043_CA55_SCLK     0   /* RZ/G2UL Only */
0033 #define R9A07G043_CA55_PCLK     1   /* RZ/G2UL Only */
0034 #define R9A07G043_CA55_ATCLK        2   /* RZ/G2UL Only */
0035 #define R9A07G043_CA55_GICCLK       3   /* RZ/G2UL Only */
0036 #define R9A07G043_CA55_PERICLK      4   /* RZ/G2UL Only */
0037 #define R9A07G043_CA55_ACLK     5   /* RZ/G2UL Only */
0038 #define R9A07G043_CA55_TSCLK        6   /* RZ/G2UL Only */
0039 #define R9A07G043_GIC600_GICCLK     7   /* RZ/G2UL Only */
0040 #define R9A07G043_IA55_CLK      8   /* RZ/G2UL Only */
0041 #define R9A07G043_IA55_PCLK     9   /* RZ/G2UL Only */
0042 #define R9A07G043_MHU_PCLK      10  /* RZ/G2UL Only */
0043 #define R9A07G043_SYC_CNT_CLK       11
0044 #define R9A07G043_DMAC_ACLK     12
0045 #define R9A07G043_DMAC_PCLK     13
0046 #define R9A07G043_OSTM0_PCLK        14
0047 #define R9A07G043_OSTM1_PCLK        15
0048 #define R9A07G043_OSTM2_PCLK        16
0049 #define R9A07G043_MTU_X_MCK_MTU3    17
0050 #define R9A07G043_POE3_CLKM_POE     18
0051 #define R9A07G043_WDT0_PCLK     19
0052 #define R9A07G043_WDT0_CLK      20
0053 #define R9A07G043_WDT2_PCLK     21  /* RZ/G2UL Only */
0054 #define R9A07G043_WDT2_CLK      22  /* RZ/G2UL Only */
0055 #define R9A07G043_SPI_CLK2      23
0056 #define R9A07G043_SPI_CLK       24
0057 #define R9A07G043_SDHI0_IMCLK       25
0058 #define R9A07G043_SDHI0_IMCLK2      26
0059 #define R9A07G043_SDHI0_CLK_HS      27
0060 #define R9A07G043_SDHI0_ACLK        28
0061 #define R9A07G043_SDHI1_IMCLK       29
0062 #define R9A07G043_SDHI1_IMCLK2      30
0063 #define R9A07G043_SDHI1_CLK_HS      31
0064 #define R9A07G043_SDHI1_ACLK        32
0065 #define R9A07G043_ISU_ACLK      33  /* RZ/G2UL Only */
0066 #define R9A07G043_ISU_PCLK      34  /* RZ/G2UL Only */
0067 #define R9A07G043_CRU_SYSCLK        35  /* RZ/G2UL Only */
0068 #define R9A07G043_CRU_VCLK      36  /* RZ/G2UL Only */
0069 #define R9A07G043_CRU_PCLK      37  /* RZ/G2UL Only */
0070 #define R9A07G043_CRU_ACLK      38  /* RZ/G2UL Only */
0071 #define R9A07G043_LCDC_CLK_A        39  /* RZ/G2UL Only */
0072 #define R9A07G043_LCDC_CLK_P        40  /* RZ/G2UL Only */
0073 #define R9A07G043_LCDC_CLK_D        41  /* RZ/G2UL Only */
0074 #define R9A07G043_SSI0_PCLK2        42
0075 #define R9A07G043_SSI0_PCLK_SFR     43
0076 #define R9A07G043_SSI1_PCLK2        44
0077 #define R9A07G043_SSI1_PCLK_SFR     45
0078 #define R9A07G043_SSI2_PCLK2        46
0079 #define R9A07G043_SSI2_PCLK_SFR     47
0080 #define R9A07G043_SSI3_PCLK2        48
0081 #define R9A07G043_SSI3_PCLK_SFR     49
0082 #define R9A07G043_SRC_CLKP      50  /* RZ/G2UL Only */
0083 #define R9A07G043_USB_U2H0_HCLK     51
0084 #define R9A07G043_USB_U2H1_HCLK     52
0085 #define R9A07G043_USB_U2P_EXR_CPUCLK    53
0086 #define R9A07G043_USB_PCLK      54
0087 #define R9A07G043_ETH0_CLK_AXI      55
0088 #define R9A07G043_ETH0_CLK_CHI      56
0089 #define R9A07G043_ETH1_CLK_AXI      57
0090 #define R9A07G043_ETH1_CLK_CHI      58
0091 #define R9A07G043_I2C0_PCLK     59
0092 #define R9A07G043_I2C1_PCLK     60
0093 #define R9A07G043_I2C2_PCLK     61
0094 #define R9A07G043_I2C3_PCLK     62
0095 #define R9A07G043_SCIF0_CLK_PCK     63
0096 #define R9A07G043_SCIF1_CLK_PCK     64
0097 #define R9A07G043_SCIF2_CLK_PCK     65
0098 #define R9A07G043_SCIF3_CLK_PCK     66
0099 #define R9A07G043_SCIF4_CLK_PCK     67
0100 #define R9A07G043_SCI0_CLKP     68
0101 #define R9A07G043_SCI1_CLKP     69
0102 #define R9A07G043_IRDA_CLKP     70
0103 #define R9A07G043_RSPI0_CLKB        71
0104 #define R9A07G043_RSPI1_CLKB        72
0105 #define R9A07G043_RSPI2_CLKB        73
0106 #define R9A07G043_CANFD_PCLK        74
0107 #define R9A07G043_GPIO_HCLK     75
0108 #define R9A07G043_ADC_ADCLK     76
0109 #define R9A07G043_ADC_PCLK      77
0110 #define R9A07G043_TSU_PCLK      78
0111 #define R9A07G043_NCEPLDM_DM_CLK    79  /* RZ/Five Only */
0112 #define R9A07G043_NCEPLDM_ACLK      80  /* RZ/Five Only */
0113 #define R9A07G043_NCEPLDM_TCK       81  /* RZ/Five Only */
0114 #define R9A07G043_NCEPLMT_ACLK      82  /* RZ/Five Only */
0115 #define R9A07G043_NCEPLIC_ACLK      83  /* RZ/Five Only */
0116 #define R9A07G043_AX45MP_CORE0_CLK  84  /* RZ/Five Only */
0117 #define R9A07G043_AX45MP_ACLK       85  /* RZ/Five Only */
0118 #define R9A07G043_IAX45_CLK     86  /* RZ/Five Only */
0119 #define R9A07G043_IAX45_PCLK        87  /* RZ/Five Only */
0120
0121 /* R9A07G043 Resets */
0122 #define R9A07G043_CA55_RST_1_0      0   /* RZ/G2UL Only */
0123 #define R9A07G043_CA55_RST_1_1      1   /* RZ/G2UL Only */
0124 #define R9A07G043_CA55_RST_3_0      2   /* RZ/G2UL Only */
0125 #define R9A07G043_CA55_RST_3_1      3   /* RZ/G2UL Only */
0126 #define R9A07G043_CA55_RST_4        4   /* RZ/G2UL Only */
0127 #define R9A07G043_CA55_RST_5        5   /* RZ/G2UL Only */
0128 #define R9A07G043_CA55_RST_6        6   /* RZ/G2UL Only */
0129 #define R9A07G043_CA55_RST_7        7   /* RZ/G2UL Only */
0130 #define R9A07G043_CA55_RST_8        8   /* RZ/G2UL Only */
0131 #define R9A07G043_CA55_RST_9        9   /* RZ/G2UL Only */
0132 #define R9A07G043_CA55_RST_10       10  /* RZ/G2UL Only */
0133 #define R9A07G043_CA55_RST_11       11  /* RZ/G2UL Only */
0134 #define R9A07G043_CA55_RST_12       12  /* RZ/G2UL Only */
0135 #define R9A07G043_GIC600_GICRESET_N 13  /* RZ/G2UL Only */
0136 #define R9A07G043_GIC600_DBG_GICRESET_N 14  /* RZ/G2UL Only */
0137 #define R9A07G043_IA55_RESETN       15  /* RZ/G2UL Only */
0138 #define R9A07G043_MHU_RESETN        16  /* RZ/G2UL Only */
0139 #define R9A07G043_DMAC_ARESETN      17
0140 #define R9A07G043_DMAC_RST_ASYNC    18
0141 #define R9A07G043_SYC_RESETN        19
0142 #define R9A07G043_OSTM0_PRESETZ     20
0143 #define R9A07G043_OSTM1_PRESETZ     21
0144 #define R9A07G043_OSTM2_PRESETZ     22
0145 #define R9A07G043_MTU_X_PRESET_MTU3 23
0146 #define R9A07G043_POE3_RST_M_REG    24
0147 #define R9A07G043_WDT0_PRESETN      25
0148 #define R9A07G043_WDT2_PRESETN      26  /* RZ/G2UL Only */
0149 #define R9A07G043_SPI_RST       27
0150 #define R9A07G043_SDHI0_IXRST       28
0151 #define R9A07G043_SDHI1_IXRST       29
0152 #define R9A07G043_ISU_ARESETN       30  /* RZ/G2UL Only */
0153 #define R9A07G043_ISU_PRESETN       31  /* RZ/G2UL Only */
0154 #define R9A07G043_CRU_CMN_RSTB      32  /* RZ/G2UL Only */
0155 #define R9A07G043_CRU_PRESETN       33  /* RZ/G2UL Only */
0156 #define R9A07G043_CRU_ARESETN       34  /* RZ/G2UL Only */
0157 #define R9A07G043_LCDC_RESET_N      35  /* RZ/G2UL Only */
0158 #define R9A07G043_SSI0_RST_M2_REG   36
0159 #define R9A07G043_SSI1_RST_M2_REG   37
0160 #define R9A07G043_SSI2_RST_M2_REG   38
0161 #define R9A07G043_SSI3_RST_M2_REG   39
0162 #define R9A07G043_SRC_RST       40  /* RZ/G2UL Only */
0163 #define R9A07G043_USB_U2H0_HRESETN  41
0164 #define R9A07G043_USB_U2H1_HRESETN  42
0165 #define R9A07G043_USB_U2P_EXL_SYSRST    43
0166 #define R9A07G043_USB_PRESETN       44
0167 #define R9A07G043_ETH0_RST_HW_N     45
0168 #define R9A07G043_ETH1_RST_HW_N     46
0169 #define R9A07G043_I2C0_MRST     47
0170 #define R9A07G043_I2C1_MRST     48
0171 #define R9A07G043_I2C2_MRST     49
0172 #define R9A07G043_I2C3_MRST     50
0173 #define R9A07G043_SCIF0_RST_SYSTEM_N    51
0174 #define R9A07G043_SCIF1_RST_SYSTEM_N    52
0175 #define R9A07G043_SCIF2_RST_SYSTEM_N    53
0176 #define R9A07G043_SCIF3_RST_SYSTEM_N    54
0177 #define R9A07G043_SCIF4_RST_SYSTEM_N    55
0178 #define R9A07G043_SCI0_RST      56
0179 #define R9A07G043_SCI1_RST      57
0180 #define R9A07G043_IRDA_RST      58
0181 #define R9A07G043_RSPI0_RST     59
0182 #define R9A07G043_RSPI1_RST     60
0183 #define R9A07G043_RSPI2_RST     61
0184 #define R9A07G043_CANFD_RSTP_N      62
0185 #define R9A07G043_CANFD_RSTC_N      63
0186 #define R9A07G043_GPIO_RSTN     64
0187 #define R9A07G043_GPIO_PORT_RESETN  65
0188 #define R9A07G043_GPIO_SPARE_RESETN 66
0189 #define R9A07G043_ADC_PRESETN       67
0190 #define R9A07G043_ADC_ADRST_N       68
0191 #define R9A07G043_TSU_PRESETN       69
0192 #define R9A07G043_NCEPLDM_DTM_PWR_RST_N 70  /* RZ/Five Only */
0193 #define R9A07G043_NCEPLDM_ARESETN   71  /* RZ/Five Only */
0194 #define R9A07G043_NCEPLMT_POR_RSTN  72  /* RZ/Five Only */
0195 #define R9A07G043_NCEPLMT_ARESETN   73  /* RZ/Five Only */
0196 #define R9A07G043_NCEPLIC_ARESETN   74  /* RZ/Five Only */
0197 #define R9A07G043_AX45MP_ARESETNM   75  /* RZ/Five Only */
0198 #define R9A07G043_AX45MP_ARESETNS   76  /* RZ/Five Only */
0199 #define R9A07G043_AX45MP_L2_RESETN  77  /* RZ/Five Only */
0200 #define R9A07G043_AX45MP_CORE0_RESETN   78  /* RZ/Five Only */
0201 #define R9A07G043_IAX45_RESETN      79  /* RZ/Five Only */
0202
0203
0204 #endif /* __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ */