dt-bindings/clock/r9a06g032-sysctrl.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * R9A06G032 sysctrl IDs
0004  *
0005  * Copyright (C) 2018 Renesas Electronics Europe Limited
0006  *
0007  * Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com>
0008  */
0009
0010 #ifndef __DT_BINDINGS_R9A06G032_SYSCTRL_H__
0011 #define __DT_BINDINGS_R9A06G032_SYSCTRL_H__
0012
0013 #define R9A06G032_CLK_PLL_USB       1
0014 #define R9A06G032_CLK_48        1   /* AKA CLK_PLL_USB */
0015 #define R9A06G032_MSEBIS_CLK        3   /* AKA CLKOUT_D16 */
0016 #define R9A06G032_MSEBIM_CLK        3   /* AKA CLKOUT_D16 */
0017 #define R9A06G032_CLK_DDRPHY_PLLCLK 5   /* AKA CLKOUT_D1OR2 */
0018 #define R9A06G032_CLK50         6   /* AKA CLKOUT_D20 */
0019 #define R9A06G032_CLK25         7   /* AKA CLKOUT_D40 */
0020 #define R9A06G032_CLK125        9   /* AKA CLKOUT_D8 */
0021 #define R9A06G032_CLK_P5_PG1        17  /* AKA DIV_P5_PG */
0022 #define R9A06G032_CLK_REF_SYNC      21  /* AKA DIV_REF_SYNC */
0023 #define R9A06G032_CLK_25_PG4        26
0024 #define R9A06G032_CLK_25_PG5        27
0025 #define R9A06G032_CLK_25_PG6        28
0026 #define R9A06G032_CLK_25_PG7        29
0027 #define R9A06G032_CLK_25_PG8        30
0028 #define R9A06G032_CLK_ADC       31
0029 #define R9A06G032_CLK_ECAT100       32
0030 #define R9A06G032_CLK_HSR100        33
0031 #define R9A06G032_CLK_I2C0      34
0032 #define R9A06G032_CLK_I2C1      35
0033 #define R9A06G032_CLK_MII_REF       36
0034 #define R9A06G032_CLK_NAND      37
0035 #define R9A06G032_CLK_NOUSBP2_PG6   38
0036 #define R9A06G032_CLK_P1_PG2        39
0037 #define R9A06G032_CLK_P1_PG3        40
0038 #define R9A06G032_CLK_P1_PG4        41
0039 #define R9A06G032_CLK_P4_PG3        42
0040 #define R9A06G032_CLK_P4_PG4        43
0041 #define R9A06G032_CLK_P6_PG1        44
0042 #define R9A06G032_CLK_P6_PG2        45
0043 #define R9A06G032_CLK_P6_PG3        46
0044 #define R9A06G032_CLK_P6_PG4        47
0045 #define R9A06G032_CLK_PCI_USB       48
0046 #define R9A06G032_CLK_QSPI0     49
0047 #define R9A06G032_CLK_QSPI1     50
0048 #define R9A06G032_CLK_RGMII_REF     51
0049 #define R9A06G032_CLK_RMII_REF      52
0050 #define R9A06G032_CLK_SDIO0     53
0051 #define R9A06G032_CLK_SDIO1     54
0052 #define R9A06G032_CLK_SERCOS100     55
0053 #define R9A06G032_CLK_SLCD      56
0054 #define R9A06G032_CLK_SPI0      57
0055 #define R9A06G032_CLK_SPI1      58
0056 #define R9A06G032_CLK_SPI2      59
0057 #define R9A06G032_CLK_SPI3      60
0058 #define R9A06G032_CLK_SPI4      61
0059 #define R9A06G032_CLK_SPI5      62
0060 #define R9A06G032_CLK_SWITCH        63
0061 #define R9A06G032_HCLK_ECAT125      65
0062 #define R9A06G032_HCLK_PINCONFIG    66
0063 #define R9A06G032_HCLK_SERCOS       67
0064 #define R9A06G032_HCLK_SGPIO2       68
0065 #define R9A06G032_HCLK_SGPIO3       69
0066 #define R9A06G032_HCLK_SGPIO4       70
0067 #define R9A06G032_HCLK_TIMER0       71
0068 #define R9A06G032_HCLK_TIMER1       72
0069 #define R9A06G032_HCLK_USBF     73
0070 #define R9A06G032_HCLK_USBH     74
0071 #define R9A06G032_HCLK_USBPM        75
0072 #define R9A06G032_CLK_48_PG_F       76
0073 #define R9A06G032_CLK_48_PG4        77
0074 #define R9A06G032_CLK_DDRPHY_PCLK   81  /* AKA CLK_REF_SYNC_D4 */
0075 #define R9A06G032_CLK_FW        81  /* AKA CLK_REF_SYNC_D4 */
0076 #define R9A06G032_CLK_CRYPTO        81  /* AKA CLK_REF_SYNC_D4 */
0077 #define R9A06G032_CLK_WATCHDOG      82  /* AKA CLK_REF_SYNC_D8 */
0078 #define R9A06G032_CLK_A7MP      84  /* AKA DIV_CA7 */
0079 #define R9A06G032_HCLK_CAN0     85
0080 #define R9A06G032_HCLK_CAN1     86
0081 #define R9A06G032_HCLK_DELTASIGMA   87
0082 #define R9A06G032_HCLK_PWMPTO       88
0083 #define R9A06G032_HCLK_RSV      89
0084 #define R9A06G032_HCLK_SGPIO0       90
0085 #define R9A06G032_HCLK_SGPIO1       91
0086 #define R9A06G032_RTOS_MDC      92
0087 #define R9A06G032_CLK_CM3       93
0088 #define R9A06G032_CLK_DDRC      94
0089 #define R9A06G032_CLK_ECAT25        95
0090 #define R9A06G032_CLK_HSR50     96
0091 #define R9A06G032_CLK_HW_RTOS       97
0092 #define R9A06G032_CLK_SERCOS50      98
0093 #define R9A06G032_HCLK_ADC      99
0094 #define R9A06G032_HCLK_CM3      100
0095 #define R9A06G032_HCLK_CRYPTO_EIP150    101
0096 #define R9A06G032_HCLK_CRYPTO_EIP93 102
0097 #define R9A06G032_HCLK_DDRC     103
0098 #define R9A06G032_HCLK_DMA0     104
0099 #define R9A06G032_HCLK_DMA1     105
0100 #define R9A06G032_HCLK_GMAC0        106
0101 #define R9A06G032_HCLK_GMAC1        107
0102 #define R9A06G032_HCLK_GPIO0        108
0103 #define R9A06G032_HCLK_GPIO1        109
0104 #define R9A06G032_HCLK_GPIO2        110
0105 #define R9A06G032_HCLK_HSR      111
0106 #define R9A06G032_HCLK_I2C0     112
0107 #define R9A06G032_HCLK_I2C1     113
0108 #define R9A06G032_HCLK_LCD      114
0109 #define R9A06G032_HCLK_MSEBI_M      115
0110 #define R9A06G032_HCLK_MSEBI_S      116
0111 #define R9A06G032_HCLK_NAND     117
0112 #define R9A06G032_HCLK_PG_I     118
0113 #define R9A06G032_HCLK_PG19     119
0114 #define R9A06G032_HCLK_PG20     120
0115 #define R9A06G032_HCLK_PG3      121
0116 #define R9A06G032_HCLK_PG4      122
0117 #define R9A06G032_HCLK_QSPI0        123
0118 #define R9A06G032_HCLK_QSPI1        124
0119 #define R9A06G032_HCLK_ROM      125
0120 #define R9A06G032_HCLK_RTC      126
0121 #define R9A06G032_HCLK_SDIO0        127
0122 #define R9A06G032_HCLK_SDIO1        128
0123 #define R9A06G032_HCLK_SEMAP        129
0124 #define R9A06G032_HCLK_SPI0     130
0125 #define R9A06G032_HCLK_SPI1     131
0126 #define R9A06G032_HCLK_SPI2     132
0127 #define R9A06G032_HCLK_SPI3     133
0128 #define R9A06G032_HCLK_SPI4     134
0129 #define R9A06G032_HCLK_SPI5     135
0130 #define R9A06G032_HCLK_SWITCH       136
0131 #define R9A06G032_HCLK_SWITCH_RG    137
0132 #define R9A06G032_HCLK_UART0        138
0133 #define R9A06G032_HCLK_UART1        139
0134 #define R9A06G032_HCLK_UART2        140
0135 #define R9A06G032_HCLK_UART3        141
0136 #define R9A06G032_HCLK_UART4        142
0137 #define R9A06G032_HCLK_UART5        143
0138 #define R9A06G032_HCLK_UART6        144
0139 #define R9A06G032_HCLK_UART7        145
0140 #define R9A06G032_CLK_UART0     146
0141 #define R9A06G032_CLK_UART1     147
0142 #define R9A06G032_CLK_UART2     148
0143 #define R9A06G032_CLK_UART3     149
0144 #define R9A06G032_CLK_UART4     150
0145 #define R9A06G032_CLK_UART5     151
0146 #define R9A06G032_CLK_UART6     152
0147 #define R9A06G032_CLK_UART7     153
0148
0149 #endif /* __DT_BINDINGS_R9A06G032_SYSCTRL_H__ */