dt-bindings/clock/r8a779g0-cpg-mssr.h

0001 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
0002 /*
0003  * Copyright (C) 2022 Renesas Electronics Corp.
0004  */
0005 #ifndef __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__
0006 #define __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__
0007
0008 #include <dt-bindings/clock/renesas-cpg-mssr.h>
0009
0010 /* r8a779g0 CPG Core Clocks */
0011
0012 #define R8A779G0_CLK_ZX         0
0013 #define R8A779G0_CLK_ZS         1
0014 #define R8A779G0_CLK_ZT         2
0015 #define R8A779G0_CLK_ZTR        3
0016 #define R8A779G0_CLK_S0D2       4
0017 #define R8A779G0_CLK_S0D3       5
0018 #define R8A779G0_CLK_S0D4       6
0019 #define R8A779G0_CLK_S0D1_VIO       7
0020 #define R8A779G0_CLK_S0D2_VIO       8
0021 #define R8A779G0_CLK_S0D4_VIO       9
0022 #define R8A779G0_CLK_S0D8_VIO       10
0023 #define R8A779G0_CLK_S0D1_VC        11
0024 #define R8A779G0_CLK_S0D2_VC        12
0025 #define R8A779G0_CLK_S0D4_VC        13
0026 #define R8A779G0_CLK_S0D2_MM        14
0027 #define R8A779G0_CLK_S0D4_MM        15
0028 #define R8A779G0_CLK_S0D2_U3DG      16
0029 #define R8A779G0_CLK_S0D4_U3DG      17
0030 #define R8A779G0_CLK_S0D2_RT        18
0031 #define R8A779G0_CLK_S0D3_RT        19
0032 #define R8A779G0_CLK_S0D4_RT        20
0033 #define R8A779G0_CLK_S0D6_RT        21
0034 #define R8A779G0_CLK_S0D24_RT       22
0035 #define R8A779G0_CLK_S0D2_PER       23
0036 #define R8A779G0_CLK_S0D3_PER       24
0037 #define R8A779G0_CLK_S0D4_PER       25
0038 #define R8A779G0_CLK_S0D6_PER       26
0039 #define R8A779G0_CLK_S0D12_PER      27
0040 #define R8A779G0_CLK_S0D24_PER      28
0041 #define R8A779G0_CLK_S0D1_HSC       29
0042 #define R8A779G0_CLK_S0D2_HSC       30
0043 #define R8A779G0_CLK_S0D4_HSC       31
0044 #define R8A779G0_CLK_S0D2_CC        32
0045 #define R8A779G0_CLK_SVD1_IR        33
0046 #define R8A779G0_CLK_SVD2_IR        34
0047 #define R8A779G0_CLK_SVD1_VIP       35
0048 #define R8A779G0_CLK_SVD2_VIP       36
0049 #define R8A779G0_CLK_CL         37
0050 #define R8A779G0_CLK_CL16M      38
0051 #define R8A779G0_CLK_CL16M_MM       39
0052 #define R8A779G0_CLK_CL16M_RT       40
0053 #define R8A779G0_CLK_CL16M_PER      41
0054 #define R8A779G0_CLK_CL16M_HSC      42
0055 #define R8A779G0_CLK_Z0         43
0056 #define R8A779G0_CLK_ZB3        44
0057 #define R8A779G0_CLK_ZB3D2      45
0058 #define R8A779G0_CLK_ZB3D4      46
0059 #define R8A779G0_CLK_ZG         47
0060 #define R8A779G0_CLK_SD0H       48
0061 #define R8A779G0_CLK_SD0        49
0062 #define R8A779G0_CLK_RPC        50
0063 #define R8A779G0_CLK_RPCD2      51
0064 #define R8A779G0_CLK_MSO        52
0065 #define R8A779G0_CLK_CANFD      53
0066 #define R8A779G0_CLK_CSI        54
0067 #define R8A779G0_CLK_FRAY       55
0068 #define R8A779G0_CLK_IPC        56
0069 #define R8A779G0_CLK_SASYNCRT       57
0070 #define R8A779G0_CLK_SASYNCPERD1    58
0071 #define R8A779G0_CLK_SASYNCPERD2    59
0072 #define R8A779G0_CLK_SASYNCPERD4    60
0073 #define R8A779G0_CLK_VIOBUS     61
0074 #define R8A779G0_CLK_VIOBUSD2       62
0075 #define R8A779G0_CLK_VCBUS      63
0076 #define R8A779G0_CLK_VCBUSD2        64
0077 #define R8A779G0_CLK_DSIEXT     65
0078 #define R8A779G0_CLK_DSIREF     66
0079 #define R8A779G0_CLK_ADGH       67
0080 #define R8A779G0_CLK_OSC        68
0081 #define R8A779G0_CLK_ZR0        69
0082 #define R8A779G0_CLK_ZR1        70
0083 #define R8A779G0_CLK_ZR2        71
0084 #define R8A779G0_CLK_IMPA       72
0085 #define R8A779G0_CLK_IMPAD4     73
0086 #define R8A779G0_CLK_CPEX       74
0087 #define R8A779G0_CLK_CBFUSA     75
0088 #define R8A779G0_CLK_R          76
0089
0090 #endif /* __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ */