dt-bindings/clock/r8a779f0-cpg-mssr.h

0001 /* SPDX-License-Identifier: (GPL-2.0 or MIT) */
0002 /*
0003  * Copyright (C) 2021 Renesas Electronics Corp.
0004  */
0005 #ifndef __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__
0006 #define __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__
0007
0008 #include <dt-bindings/clock/renesas-cpg-mssr.h>
0009
0010 /* r8a779f0 CPG Core Clocks */
0011
0012 #define R8A779F0_CLK_ZX         0
0013 #define R8A779F0_CLK_ZS         1
0014 #define R8A779F0_CLK_ZT         2
0015 #define R8A779F0_CLK_ZTR        3
0016 #define R8A779F0_CLK_S0D2       4
0017 #define R8A779F0_CLK_S0D3       5
0018 #define R8A779F0_CLK_S0D4       6
0019 #define R8A779F0_CLK_S0D2_MM        7
0020 #define R8A779F0_CLK_S0D3_MM        8
0021 #define R8A779F0_CLK_S0D4_MM        9
0022 #define R8A779F0_CLK_S0D2_RT        10
0023 #define R8A779F0_CLK_S0D3_RT        11
0024 #define R8A779F0_CLK_S0D4_RT        12
0025 #define R8A779F0_CLK_S0D6_RT        13
0026 #define R8A779F0_CLK_S0D3_PER       14
0027 #define R8A779F0_CLK_S0D6_PER       15
0028 #define R8A779F0_CLK_S0D12_PER      16
0029 #define R8A779F0_CLK_S0D24_PER      17
0030 #define R8A779F0_CLK_S0D2_HSC       18
0031 #define R8A779F0_CLK_S0D3_HSC       19
0032 #define R8A779F0_CLK_S0D4_HSC       20
0033 #define R8A779F0_CLK_S0D6_HSC       21
0034 #define R8A779F0_CLK_S0D12_HSC      22
0035 #define R8A779F0_CLK_S0D2_CC        23
0036 #define R8A779F0_CLK_CL         24
0037 #define R8A779F0_CLK_CL16M      25
0038 #define R8A779F0_CLK_CL16M_MM       26
0039 #define R8A779F0_CLK_CL16M_RT       27
0040 #define R8A779F0_CLK_CL16M_PER      28
0041 #define R8A779F0_CLK_CL16M_HSC      29
0042 #define R8A779F0_CLK_Z0         30
0043 #define R8A779F0_CLK_Z1         31
0044 #define R8A779F0_CLK_ZB3        32
0045 #define R8A779F0_CLK_ZB3D2      33
0046 #define R8A779F0_CLK_ZB3D4      34
0047 #define R8A779F0_CLK_SD0H       35
0048 #define R8A779F0_CLK_SD0        36
0049 #define R8A779F0_CLK_RPC        37
0050 #define R8A779F0_CLK_RPCD2      38
0051 #define R8A779F0_CLK_MSO        39
0052 #define R8A779F0_CLK_SASYNCRT       40
0053 #define R8A779F0_CLK_SASYNCPERD1    41
0054 #define R8A779F0_CLK_SASYNCPERD2    42
0055 #define R8A779F0_CLK_SASYNCPERD4    43
0056 #define R8A779F0_CLK_DBGSOC_HSC     44
0057 #define R8A779F0_CLK_RSW2       45
0058 #define R8A779F0_CLK_OSC        46
0059 #define R8A779F0_CLK_ZR         47
0060 #define R8A779F0_CLK_CPEX       48
0061 #define R8A779F0_CLK_CBFUSA     49
0062 #define R8A779F0_CLK_R          50
0063
0064 #endif /* __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__ */