dt-bindings/clock/r8a77990-cpg-mssr.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (C) 2018 Renesas Electronics Corp.
0004  */
0005 #ifndef __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
0006 #define __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
0007
0008 #include <dt-bindings/clock/renesas-cpg-mssr.h>
0009
0010 /* r8a77990 CPG Core Clocks */
0011 #define R8A77990_CLK_Z2         0
0012 #define R8A77990_CLK_ZR         1
0013 #define R8A77990_CLK_ZG         2
0014 #define R8A77990_CLK_ZTR        3
0015 #define R8A77990_CLK_ZT         4
0016 #define R8A77990_CLK_ZX         5
0017 #define R8A77990_CLK_S0D1       6
0018 #define R8A77990_CLK_S0D3       7
0019 #define R8A77990_CLK_S0D6       8
0020 #define R8A77990_CLK_S0D12      9
0021 #define R8A77990_CLK_S0D24      10
0022 #define R8A77990_CLK_S1D1       11
0023 #define R8A77990_CLK_S1D2       12
0024 #define R8A77990_CLK_S1D4       13
0025 #define R8A77990_CLK_S2D1       14
0026 #define R8A77990_CLK_S2D2       15
0027 #define R8A77990_CLK_S2D4       16
0028 #define R8A77990_CLK_S3D1       17
0029 #define R8A77990_CLK_S3D2       18
0030 #define R8A77990_CLK_S3D4       19
0031 #define R8A77990_CLK_S0D6C      20
0032 #define R8A77990_CLK_S3D1C      21
0033 #define R8A77990_CLK_S3D2C      22
0034 #define R8A77990_CLK_S3D4C      23
0035 #define R8A77990_CLK_LB         24
0036 #define R8A77990_CLK_CL         25
0037 #define R8A77990_CLK_ZB3        26
0038 #define R8A77990_CLK_ZB3D2      27
0039 #define R8A77990_CLK_CR         28
0040 #define R8A77990_CLK_CRD2       29
0041 #define R8A77990_CLK_SD0H       30
0042 #define R8A77990_CLK_SD0        31
0043 #define R8A77990_CLK_SD1H       32
0044 #define R8A77990_CLK_SD1        33
0045 #define R8A77990_CLK_SD3H       34
0046 #define R8A77990_CLK_SD3        35
0047 #define R8A77990_CLK_RPC        36
0048 #define R8A77990_CLK_RPCD2      37
0049 #define R8A77990_CLK_ZA2        38
0050 #define R8A77990_CLK_ZA8        39
0051 #define R8A77990_CLK_Z2D        40
0052 #define R8A77990_CLK_CANFD      41
0053 #define R8A77990_CLK_MSO        42
0054 #define R8A77990_CLK_R          43
0055 #define R8A77990_CLK_OSC        44
0056 #define R8A77990_CLK_LV0        45
0057 #define R8A77990_CLK_LV1        46
0058 #define R8A77990_CLK_CSI0       47
0059 #define R8A77990_CLK_CP         48
0060 #define R8A77990_CLK_CPEX       49
0061
0062 #endif /* __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ */