dt-bindings/clock/r8a77980-cpg-mssr.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * Copyright (C) 2018 Renesas Electronics Corp.
0004  * Copyright (C) 2018 Cogent Embedded, Inc.
0005  */
0006 #ifndef __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__
0007 #define __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__
0008
0009 #include <dt-bindings/clock/renesas-cpg-mssr.h>
0010
0011 /* r8a77980 CPG Core Clocks */
0012 #define R8A77980_CLK_Z2         0
0013 #define R8A77980_CLK_ZR         1
0014 #define R8A77980_CLK_ZTR        2
0015 #define R8A77980_CLK_ZTRD2      3
0016 #define R8A77980_CLK_ZT         4
0017 #define R8A77980_CLK_ZX         5
0018 #define R8A77980_CLK_S0D1       6
0019 #define R8A77980_CLK_S0D2       7
0020 #define R8A77980_CLK_S0D3       8
0021 #define R8A77980_CLK_S0D4       9
0022 #define R8A77980_CLK_S0D6       10
0023 #define R8A77980_CLK_S0D12      11
0024 #define R8A77980_CLK_S0D24      12
0025 #define R8A77980_CLK_S1D1       13
0026 #define R8A77980_CLK_S1D2       14
0027 #define R8A77980_CLK_S1D4       15
0028 #define R8A77980_CLK_S2D1       16
0029 #define R8A77980_CLK_S2D2       17
0030 #define R8A77980_CLK_S2D4       18
0031 #define R8A77980_CLK_S3D1       19
0032 #define R8A77980_CLK_S3D2       20
0033 #define R8A77980_CLK_S3D4       21
0034 #define R8A77980_CLK_LB         22
0035 #define R8A77980_CLK_CL         23
0036 #define R8A77980_CLK_ZB3        24
0037 #define R8A77980_CLK_ZB3D2      25
0038 #define R8A77980_CLK_ZB3D4      26
0039 #define R8A77980_CLK_SD0H       27
0040 #define R8A77980_CLK_SD0        28
0041 #define R8A77980_CLK_RPC        29
0042 #define R8A77980_CLK_RPCD2      30
0043 #define R8A77980_CLK_MSO        31
0044 #define R8A77980_CLK_CANFD      32
0045 #define R8A77980_CLK_CSI0       33
0046 #define R8A77980_CLK_CP         34
0047 #define R8A77980_CLK_CPEX       35
0048 #define R8A77980_CLK_R          36
0049 #define R8A77980_CLK_OSC        37
0050
0051 #endif /* __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ */