dt-bindings/clock/r8a77970-cpg-mssr.h

0001 /* SPDX-License-Identifier: GPL-2.0+
0002  *
0003  * Copyright (C) 2016 Renesas Electronics Corp.
0004  * Copyright (C) 2017 Cogent Embedded, Inc.
0005  */
0006 #ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
0007 #define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
0008
0009 #include <dt-bindings/clock/renesas-cpg-mssr.h>
0010
0011 /* r8a77970 CPG Core Clocks */
0012 #define R8A77970_CLK_Z2         0
0013 #define R8A77970_CLK_ZR         1
0014 #define R8A77970_CLK_ZTR        2
0015 #define R8A77970_CLK_ZTRD2      3
0016 #define R8A77970_CLK_ZT         4
0017 #define R8A77970_CLK_ZX         5
0018 #define R8A77970_CLK_S1D1       6
0019 #define R8A77970_CLK_S1D2       7
0020 #define R8A77970_CLK_S1D4       8
0021 #define R8A77970_CLK_S2D1       9
0022 #define R8A77970_CLK_S2D2       10
0023 #define R8A77970_CLK_S2D4       11
0024 #define R8A77970_CLK_LB         12
0025 #define R8A77970_CLK_CL         13
0026 #define R8A77970_CLK_ZB3        14
0027 #define R8A77970_CLK_ZB3D2      15
0028 #define R8A77970_CLK_DDR        16
0029 #define R8A77970_CLK_CR         17
0030 #define R8A77970_CLK_CRD2       18
0031 #define R8A77970_CLK_SD0H       19
0032 #define R8A77970_CLK_SD0        20
0033 #define R8A77970_CLK_RPC        21
0034 #define R8A77970_CLK_RPCD2      22
0035 #define R8A77970_CLK_MSO        23
0036 #define R8A77970_CLK_CANFD      24
0037 #define R8A77970_CLK_CSI0       25
0038 #define R8A77970_CLK_FRAY       26
0039 #define R8A77970_CLK_CP         27
0040 #define R8A77970_CLK_CPEX       28
0041 #define R8A77970_CLK_R          29
0042 #define R8A77970_CLK_OSC        30
0043
0044 #endif /* __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ */