dt-bindings/clock/r8a77961-cpg-mssr.h

0001 /* SPDX-License-Identifier: GPL-2.0+
0002  *
0003  * Copyright (C) 2019 Renesas Electronics Corp.
0004  */
0005 #ifndef __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__
0006 #define __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__
0007
0008 #include <dt-bindings/clock/renesas-cpg-mssr.h>
0009
0010 /* r8a77961 CPG Core Clocks */
0011 #define R8A77961_CLK_Z          0
0012 #define R8A77961_CLK_Z2         1
0013 #define R8A77961_CLK_ZR         2
0014 #define R8A77961_CLK_ZG         3
0015 #define R8A77961_CLK_ZTR            4
0016 #define R8A77961_CLK_ZTRD2      5
0017 #define R8A77961_CLK_ZT         6
0018 #define R8A77961_CLK_ZX         7
0019 #define R8A77961_CLK_S0D1       8
0020 #define R8A77961_CLK_S0D2       9
0021 #define R8A77961_CLK_S0D3       10
0022 #define R8A77961_CLK_S0D4       11
0023 #define R8A77961_CLK_S0D6       12
0024 #define R8A77961_CLK_S0D8       13
0025 #define R8A77961_CLK_S0D12      14
0026 #define R8A77961_CLK_S1D1       15
0027 #define R8A77961_CLK_S1D2       16
0028 #define R8A77961_CLK_S1D4       17
0029 #define R8A77961_CLK_S2D1       18
0030 #define R8A77961_CLK_S2D2       19
0031 #define R8A77961_CLK_S2D4       20
0032 #define R8A77961_CLK_S3D1       21
0033 #define R8A77961_CLK_S3D2       22
0034 #define R8A77961_CLK_S3D4       23
0035 #define R8A77961_CLK_LB         24
0036 #define R8A77961_CLK_CL         25
0037 #define R8A77961_CLK_ZB3            26
0038 #define R8A77961_CLK_ZB3D2      27
0039 #define R8A77961_CLK_ZB3D4      28
0040 #define R8A77961_CLK_CR         29
0041 #define R8A77961_CLK_CRD2       30
0042 #define R8A77961_CLK_SD0H       31
0043 #define R8A77961_CLK_SD0            32
0044 #define R8A77961_CLK_SD1H       33
0045 #define R8A77961_CLK_SD1            34
0046 #define R8A77961_CLK_SD2H       35
0047 #define R8A77961_CLK_SD2            36
0048 #define R8A77961_CLK_SD3H       37
0049 #define R8A77961_CLK_SD3            38
0050 #define R8A77961_CLK_SSP2       39
0051 #define R8A77961_CLK_SSP1       40
0052 #define R8A77961_CLK_SSPRS      41
0053 #define R8A77961_CLK_RPC            42
0054 #define R8A77961_CLK_RPCD2      43
0055 #define R8A77961_CLK_MSO            44
0056 #define R8A77961_CLK_CANFD      45
0057 #define R8A77961_CLK_HDMI       46
0058 #define R8A77961_CLK_CSI0       47
0059 /* CLK_CSIREF was removed */
0060 #define R8A77961_CLK_CP         49
0061 #define R8A77961_CLK_CPEX       50
0062 #define R8A77961_CLK_R          51
0063 #define R8A77961_CLK_OSC            52
0064
0065 #endif /* __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__ */