dt-bindings/clock/r8a7795-cpg-mssr.h

0001 /* SPDX-License-Identifier: GPL-2.0+
0002  *
0003  * Copyright (C) 2015 Renesas Electronics Corp.
0004  */
0005 #ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
0006 #define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
0007
0008 #include <dt-bindings/clock/renesas-cpg-mssr.h>
0009
0010 /* r8a7795 CPG Core Clocks */
0011 #define R8A7795_CLK_Z           0
0012 #define R8A7795_CLK_Z2          1
0013 #define R8A7795_CLK_ZR          2
0014 #define R8A7795_CLK_ZG          3
0015 #define R8A7795_CLK_ZTR         4
0016 #define R8A7795_CLK_ZTRD2       5
0017 #define R8A7795_CLK_ZT          6
0018 #define R8A7795_CLK_ZX          7
0019 #define R8A7795_CLK_S0D1        8
0020 #define R8A7795_CLK_S0D4        9
0021 #define R8A7795_CLK_S1D1        10
0022 #define R8A7795_CLK_S1D2        11
0023 #define R8A7795_CLK_S1D4        12
0024 #define R8A7795_CLK_S2D1        13
0025 #define R8A7795_CLK_S2D2        14
0026 #define R8A7795_CLK_S2D4        15
0027 #define R8A7795_CLK_S3D1        16
0028 #define R8A7795_CLK_S3D2        17
0029 #define R8A7795_CLK_S3D4        18
0030 #define R8A7795_CLK_LB          19
0031 #define R8A7795_CLK_CL          20
0032 #define R8A7795_CLK_ZB3         21
0033 #define R8A7795_CLK_ZB3D2       22
0034 #define R8A7795_CLK_CR          23
0035 #define R8A7795_CLK_CRD2        24
0036 #define R8A7795_CLK_SD0H        25
0037 #define R8A7795_CLK_SD0         26
0038 #define R8A7795_CLK_SD1H        27
0039 #define R8A7795_CLK_SD1         28
0040 #define R8A7795_CLK_SD2H        29
0041 #define R8A7795_CLK_SD2         30
0042 #define R8A7795_CLK_SD3H        31
0043 #define R8A7795_CLK_SD3         32
0044 #define R8A7795_CLK_SSP2        33
0045 #define R8A7795_CLK_SSP1        34
0046 #define R8A7795_CLK_SSPRS       35
0047 #define R8A7795_CLK_RPC         36
0048 #define R8A7795_CLK_RPCD2       37
0049 #define R8A7795_CLK_MSO         38
0050 #define R8A7795_CLK_CANFD       39
0051 #define R8A7795_CLK_HDMI        40
0052 #define R8A7795_CLK_CSI0        41
0053 /* CLK_CSIREF was removed */
0054 #define R8A7795_CLK_CP          43
0055 #define R8A7795_CLK_CPEX        44
0056 #define R8A7795_CLK_R           45
0057 #define R8A7795_CLK_OSC         46
0058
0059 /* r8a7795 ES2.0 CPG Core Clocks */
0060 #define R8A7795_CLK_S0D2        47
0061 #define R8A7795_CLK_S0D3        48
0062 #define R8A7795_CLK_S0D6        49
0063 #define R8A7795_CLK_S0D8        50
0064 #define R8A7795_CLK_S0D12       51
0065
0066 #endif /* __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ */