dt-bindings/clock/r8a7794-cpg-mssr.h

0001 /* SPDX-License-Identifier: GPL-2.0+
0002  *
0003  * Copyright (C) 2015 Renesas Electronics Corp.
0004  */
0005
0006 #ifndef __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__
0007 #define __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__
0008
0009 #include <dt-bindings/clock/renesas-cpg-mssr.h>
0010
0011 /* r8a7794 CPG Core Clocks */
0012 #define R8A7794_CLK_Z2          0
0013 #define R8A7794_CLK_ZG          1
0014 #define R8A7794_CLK_ZTR         2
0015 #define R8A7794_CLK_ZTRD2       3
0016 #define R8A7794_CLK_ZT          4
0017 #define R8A7794_CLK_ZX          5
0018 #define R8A7794_CLK_ZS          6
0019 #define R8A7794_CLK_HP          7
0020 #define R8A7794_CLK_I           8
0021 #define R8A7794_CLK_B           9
0022 #define R8A7794_CLK_LB          10
0023 #define R8A7794_CLK_P           11
0024 #define R8A7794_CLK_CL          12
0025 #define R8A7794_CLK_CP          13
0026 #define R8A7794_CLK_M2          14
0027 #define R8A7794_CLK_ADSP        15
0028 #define R8A7794_CLK_ZB3         16
0029 #define R8A7794_CLK_ZB3D2       17
0030 #define R8A7794_CLK_DDR         18
0031 #define R8A7794_CLK_SDH         19
0032 #define R8A7794_CLK_SD0         20
0033 #define R8A7794_CLK_SD2         21
0034 #define R8A7794_CLK_SD3         22
0035 #define R8A7794_CLK_MMC0        23
0036 #define R8A7794_CLK_MP          24
0037 #define R8A7794_CLK_QSPI        25
0038 #define R8A7794_CLK_CPEX        26
0039 #define R8A7794_CLK_RCAN        27
0040 #define R8A7794_CLK_R           28
0041 #define R8A7794_CLK_OSC         29
0042
0043 #endif /* __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ */