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0001 /* SPDX-License-Identifier: GPL-2.0+
0002  *
0003  * Copyright (C) 2014 Renesas Electronics Corporation
0004  * Copyright 2013 Ideas On Board SPRL
0005  */
0006 
0007 #ifndef __DT_BINDINGS_CLOCK_R8A7794_H__
0008 #define __DT_BINDINGS_CLOCK_R8A7794_H__
0009 
0010 /* CPG */
0011 #define R8A7794_CLK_MAIN        0
0012 #define R8A7794_CLK_PLL0        1
0013 #define R8A7794_CLK_PLL1        2
0014 #define R8A7794_CLK_PLL3        3
0015 #define R8A7794_CLK_LB          4
0016 #define R8A7794_CLK_QSPI        5
0017 #define R8A7794_CLK_SDH         6
0018 #define R8A7794_CLK_SD0         7
0019 #define R8A7794_CLK_RCAN        8
0020 
0021 /* MSTP0 */
0022 #define R8A7794_CLK_MSIOF0      0
0023 
0024 /* MSTP1 */
0025 #define R8A7794_CLK_VCP0        1
0026 #define R8A7794_CLK_VPC0        3
0027 #define R8A7794_CLK_TMU1        11
0028 #define R8A7794_CLK_3DG         12
0029 #define R8A7794_CLK_2DDMAC      15
0030 #define R8A7794_CLK_FDP1_0      19
0031 #define R8A7794_CLK_TMU3        21
0032 #define R8A7794_CLK_TMU2        22
0033 #define R8A7794_CLK_CMT0        24
0034 #define R8A7794_CLK_TMU0        25
0035 #define R8A7794_CLK_VSP1_DU0        28
0036 #define R8A7794_CLK_VSP1_S      31
0037 
0038 /* MSTP2 */
0039 #define R8A7794_CLK_SCIFA2      2
0040 #define R8A7794_CLK_SCIFA1      3
0041 #define R8A7794_CLK_SCIFA0      4
0042 #define R8A7794_CLK_MSIOF2      5
0043 #define R8A7794_CLK_SCIFB0      6
0044 #define R8A7794_CLK_SCIFB1      7
0045 #define R8A7794_CLK_MSIOF1      8
0046 #define R8A7794_CLK_SCIFB2      16
0047 #define R8A7794_CLK_SYS_DMAC1       18
0048 #define R8A7794_CLK_SYS_DMAC0       19
0049 
0050 /* MSTP3 */
0051 #define R8A7794_CLK_SDHI2       11
0052 #define R8A7794_CLK_SDHI1       12
0053 #define R8A7794_CLK_SDHI0       14
0054 #define R8A7794_CLK_MMCIF0      15
0055 #define R8A7794_CLK_IIC0        18
0056 #define R8A7794_CLK_IIC1        23
0057 #define R8A7794_CLK_CMT1        29
0058 #define R8A7794_CLK_USBDMAC0        30
0059 #define R8A7794_CLK_USBDMAC1        31
0060 
0061 /* MSTP4 */
0062 #define R8A7794_CLK_IRQC        7
0063 #define R8A7794_CLK_INTC_SYS        8
0064 
0065 /* MSTP5 */
0066 #define R8A7794_CLK_AUDIO_DMAC0     2
0067 #define R8A7794_CLK_PWM         23
0068 
0069 /* MSTP7 */
0070 #define R8A7794_CLK_EHCI        3
0071 #define R8A7794_CLK_HSUSB       4
0072 #define R8A7794_CLK_HSCIF2      13
0073 #define R8A7794_CLK_SCIF5       14
0074 #define R8A7794_CLK_SCIF4       15
0075 #define R8A7794_CLK_HSCIF1      16
0076 #define R8A7794_CLK_HSCIF0      17
0077 #define R8A7794_CLK_SCIF3       18
0078 #define R8A7794_CLK_SCIF2       19
0079 #define R8A7794_CLK_SCIF1       20
0080 #define R8A7794_CLK_SCIF0       21
0081 #define R8A7794_CLK_DU1         23
0082 #define R8A7794_CLK_DU0         24
0083 
0084 /* MSTP8 */
0085 #define R8A7794_CLK_VIN1        10
0086 #define R8A7794_CLK_VIN0        11
0087 #define R8A7794_CLK_ETHERAVB        12
0088 #define R8A7794_CLK_ETHER       13
0089 
0090 /* MSTP9 */
0091 #define R8A7794_CLK_GPIO6       5
0092 #define R8A7794_CLK_GPIO5       7
0093 #define R8A7794_CLK_GPIO4       8
0094 #define R8A7794_CLK_GPIO3       9
0095 #define R8A7794_CLK_GPIO2       10
0096 #define R8A7794_CLK_GPIO1       11
0097 #define R8A7794_CLK_GPIO0       12
0098 #define R8A7794_CLK_RCAN1       15
0099 #define R8A7794_CLK_RCAN0       16
0100 #define R8A7794_CLK_QSPI_MOD        17
0101 #define R8A7794_CLK_I2C5        25
0102 #define R8A7794_CLK_I2C4        27
0103 #define R8A7794_CLK_I2C3        28
0104 #define R8A7794_CLK_I2C2        29
0105 #define R8A7794_CLK_I2C1        30
0106 #define R8A7794_CLK_I2C0        31
0107 
0108 /* MSTP10 */
0109 #define R8A7794_CLK_SSI_ALL     5
0110 #define R8A7794_CLK_SSI9        6
0111 #define R8A7794_CLK_SSI8        7
0112 #define R8A7794_CLK_SSI7        8
0113 #define R8A7794_CLK_SSI6        9
0114 #define R8A7794_CLK_SSI5        10
0115 #define R8A7794_CLK_SSI4        11
0116 #define R8A7794_CLK_SSI3        12
0117 #define R8A7794_CLK_SSI2        13
0118 #define R8A7794_CLK_SSI1        14
0119 #define R8A7794_CLK_SSI0        15
0120 #define R8A7794_CLK_SCU_ALL     17
0121 #define R8A7794_CLK_SCU_DVC1        18
0122 #define R8A7794_CLK_SCU_DVC0        19
0123 #define R8A7794_CLK_SCU_CTU1_MIX1   20
0124 #define R8A7794_CLK_SCU_CTU0_MIX0   21
0125 #define R8A7794_CLK_SCU_SRC6        25
0126 #define R8A7794_CLK_SCU_SRC5        26
0127 #define R8A7794_CLK_SCU_SRC4        27
0128 #define R8A7794_CLK_SCU_SRC3        28
0129 #define R8A7794_CLK_SCU_SRC2        29
0130 #define R8A7794_CLK_SCU_SRC1        30
0131 
0132 /* MSTP11 */
0133 #define R8A7794_CLK_SCIFA3      6
0134 #define R8A7794_CLK_SCIFA4      7
0135 #define R8A7794_CLK_SCIFA5      8
0136 
0137 #endif /* __DT_BINDINGS_CLOCK_R8A7794_H__ */