dt-bindings/clock/r8a7792-clock.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright (C) 2016 Cogent Embedded, Inc.
0004  */
0005
0006 #ifndef __DT_BINDINGS_CLOCK_R8A7792_H__
0007 #define __DT_BINDINGS_CLOCK_R8A7792_H__
0008
0009 /* CPG */
0010 #define R8A7792_CLK_MAIN        0
0011 #define R8A7792_CLK_PLL0        1
0012 #define R8A7792_CLK_PLL1        2
0013 #define R8A7792_CLK_PLL3        3
0014 #define R8A7792_CLK_LB          4
0015 #define R8A7792_CLK_QSPI        5
0016
0017 /* MSTP0 */
0018 #define R8A7792_CLK_MSIOF0      0
0019
0020 /* MSTP1 */
0021 #define R8A7792_CLK_JPU         6
0022 #define R8A7792_CLK_TMU1        11
0023 #define R8A7792_CLK_TMU3        21
0024 #define R8A7792_CLK_TMU2        22
0025 #define R8A7792_CLK_CMT0        24
0026 #define R8A7792_CLK_TMU0        25
0027 #define R8A7792_CLK_VSP1DU1     27
0028 #define R8A7792_CLK_VSP1DU0     28
0029 #define R8A7792_CLK_VSP1_SY     31
0030
0031 /* MSTP2 */
0032 #define R8A7792_CLK_MSIOF1      8
0033 #define R8A7792_CLK_SYS_DMAC1       18
0034 #define R8A7792_CLK_SYS_DMAC0       19
0035
0036 /* MSTP3 */
0037 #define R8A7792_CLK_TPU0        4
0038 #define R8A7792_CLK_SDHI0       14
0039 #define R8A7792_CLK_CMT1        29
0040
0041 /* MSTP4 */
0042 #define R8A7792_CLK_IRQC        7
0043 #define R8A7792_CLK_INTC_SYS        8
0044
0045 /* MSTP5 */
0046 #define R8A7792_CLK_AUDIO_DMAC0     2
0047 #define R8A7792_CLK_THERMAL     22
0048 #define R8A7792_CLK_PWM         23
0049
0050 /* MSTP7 */
0051 #define R8A7792_CLK_HSCIF1      16
0052 #define R8A7792_CLK_HSCIF0      17
0053 #define R8A7792_CLK_SCIF3       18
0054 #define R8A7792_CLK_SCIF2       19
0055 #define R8A7792_CLK_SCIF1       20
0056 #define R8A7792_CLK_SCIF0       21
0057 #define R8A7792_CLK_DU1         23
0058 #define R8A7792_CLK_DU0         24
0059
0060 /* MSTP8 */
0061 #define R8A7792_CLK_VIN5        4
0062 #define R8A7792_CLK_VIN4        5
0063 #define R8A7792_CLK_VIN3        8
0064 #define R8A7792_CLK_VIN2        9
0065 #define R8A7792_CLK_VIN1        10
0066 #define R8A7792_CLK_VIN0        11
0067 #define R8A7792_CLK_ETHERAVB        12
0068
0069 /* MSTP9 */
0070 #define R8A7792_CLK_GPIO7       4
0071 #define R8A7792_CLK_GPIO6       5
0072 #define R8A7792_CLK_GPIO5       7
0073 #define R8A7792_CLK_GPIO4       8
0074 #define R8A7792_CLK_GPIO3       9
0075 #define R8A7792_CLK_GPIO2       10
0076 #define R8A7792_CLK_GPIO1       11
0077 #define R8A7792_CLK_GPIO0       12
0078 #define R8A7792_CLK_GPIO11      13
0079 #define R8A7792_CLK_GPIO10      14
0080 #define R8A7792_CLK_CAN1        15
0081 #define R8A7792_CLK_CAN0        16
0082 #define R8A7792_CLK_QSPI_MOD        17
0083 #define R8A7792_CLK_GPIO9       19
0084 #define R8A7792_CLK_GPIO8       21
0085 #define R8A7792_CLK_I2C5        25
0086 #define R8A7792_CLK_IICDVFS     26
0087 #define R8A7792_CLK_I2C4        27
0088 #define R8A7792_CLK_I2C3        28
0089 #define R8A7792_CLK_I2C2        29
0090 #define R8A7792_CLK_I2C1        30
0091 #define R8A7792_CLK_I2C0        31
0092
0093 /* MSTP10 */
0094 #define R8A7792_CLK_SSI_ALL     5
0095 #define R8A7792_CLK_SSI4        11
0096 #define R8A7792_CLK_SSI3        12
0097
0098 #endif /* __DT_BINDINGS_CLOCK_R8A7792_H__ */