dt-bindings/clock/r8a7790-cpg-mssr.h

0001 /* SPDX-License-Identifier: GPL-2.0+
0002  *
0003  * Copyright (C) 2015 Renesas Electronics Corp.
0004  */
0005
0006 #ifndef __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
0007 #define __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
0008
0009 #include <dt-bindings/clock/renesas-cpg-mssr.h>
0010
0011 /* r8a7790 CPG Core Clocks */
0012 #define R8A7790_CLK_Z           0
0013 #define R8A7790_CLK_Z2          1
0014 #define R8A7790_CLK_ZG          2
0015 #define R8A7790_CLK_ZTR         3
0016 #define R8A7790_CLK_ZTRD2       4
0017 #define R8A7790_CLK_ZT          5
0018 #define R8A7790_CLK_ZX          6
0019 #define R8A7790_CLK_ZS          7
0020 #define R8A7790_CLK_HP          8
0021 #define R8A7790_CLK_I           9
0022 #define R8A7790_CLK_B           10
0023 #define R8A7790_CLK_LB          11
0024 #define R8A7790_CLK_P           12
0025 #define R8A7790_CLK_CL          13
0026 #define R8A7790_CLK_M2          14
0027 #define R8A7790_CLK_ADSP        15
0028 #define R8A7790_CLK_IMP         16
0029 #define R8A7790_CLK_ZB3         17
0030 #define R8A7790_CLK_ZB3D2       18
0031 #define R8A7790_CLK_DDR         19
0032 #define R8A7790_CLK_SDH         20
0033 #define R8A7790_CLK_SD0         21
0034 #define R8A7790_CLK_SD1         22
0035 #define R8A7790_CLK_SD2         23
0036 #define R8A7790_CLK_SD3         24
0037 #define R8A7790_CLK_MMC0        25
0038 #define R8A7790_CLK_MMC1        26
0039 #define R8A7790_CLK_MP          27
0040 #define R8A7790_CLK_SSP         28
0041 #define R8A7790_CLK_SSPRS       29
0042 #define R8A7790_CLK_QSPI        30
0043 #define R8A7790_CLK_CP          31
0044 #define R8A7790_CLK_RCAN        32
0045 #define R8A7790_CLK_R           33
0046 #define R8A7790_CLK_OSC         34
0047
0048 #endif /* __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ */