dt-bindings/clock/r8a77470-cpg-mssr.h

0001 /* SPDX-License-Identifier: GPL-2.0
0002  *
0003  * Copyright (C) 2018 Renesas Electronics Corp.
0004  */
0005 #ifndef __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__
0006 #define __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__
0007
0008 #include <dt-bindings/clock/renesas-cpg-mssr.h>
0009
0010 /* r8a77470 CPG Core Clocks */
0011 #define R8A77470_CLK_Z2     0
0012 #define R8A77470_CLK_ZTR    1
0013 #define R8A77470_CLK_ZTRD2  2
0014 #define R8A77470_CLK_ZT     3
0015 #define R8A77470_CLK_ZX     4
0016 #define R8A77470_CLK_ZS     5
0017 #define R8A77470_CLK_HP     6
0018 #define R8A77470_CLK_B      7
0019 #define R8A77470_CLK_LB     8
0020 #define R8A77470_CLK_P      9
0021 #define R8A77470_CLK_CL     10
0022 #define R8A77470_CLK_CP     11
0023 #define R8A77470_CLK_M2     12
0024 #define R8A77470_CLK_ZB3    13
0025 #define R8A77470_CLK_SDH    14
0026 #define R8A77470_CLK_SD0    15
0027 #define R8A77470_CLK_SD1    16
0028 #define R8A77470_CLK_SD2    17
0029 #define R8A77470_CLK_MP     18
0030 #define R8A77470_CLK_QSPI   19
0031 #define R8A77470_CLK_CPEX   20
0032 #define R8A77470_CLK_RCAN   21
0033 #define R8A77470_CLK_R      22
0034 #define R8A77470_CLK_OSC    23
0035
0036 #endif /* __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ */