dt-bindings/clock/r8a7744-cpg-mssr.h

0001 /* SPDX-License-Identifier: GPL-2.0
0002  *
0003  * Copyright (C) 2018 Renesas Electronics Corp.
0004  */
0005 #ifndef __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H__
0006 #define __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H__
0007
0008 #include <dt-bindings/clock/renesas-cpg-mssr.h>
0009
0010 /* r8a7744 CPG Core Clocks */
0011 #define R8A7744_CLK_Z       0
0012 #define R8A7744_CLK_ZG      1
0013 #define R8A7744_CLK_ZTR     2
0014 #define R8A7744_CLK_ZTRD2   3
0015 #define R8A7744_CLK_ZT      4
0016 #define R8A7744_CLK_ZX      5
0017 #define R8A7744_CLK_ZS      6
0018 #define R8A7744_CLK_HP      7
0019 #define R8A7744_CLK_B       9
0020 #define R8A7744_CLK_LB      10
0021 #define R8A7744_CLK_P       11
0022 #define R8A7744_CLK_CL      12
0023 #define R8A7744_CLK_M2      13
0024 #define R8A7744_CLK_ZB3     15
0025 #define R8A7744_CLK_ZB3D2   16
0026 #define R8A7744_CLK_DDR     17
0027 #define R8A7744_CLK_SDH     18
0028 #define R8A7744_CLK_SD0     19
0029 #define R8A7744_CLK_SD2     20
0030 #define R8A7744_CLK_SD3     21
0031 #define R8A7744_CLK_MMC0    22
0032 #define R8A7744_CLK_MP      23
0033 #define R8A7744_CLK_QSPI    26
0034 #define R8A7744_CLK_CP      27
0035 #define R8A7744_CLK_RCAN    28
0036 #define R8A7744_CLK_R       29
0037 #define R8A7744_CLK_OSC     30
0038
0039 #endif /* __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H__ */