dt-bindings/clock/r8a7742-cpg-mssr.h

0001 /* SPDX-License-Identifier: GPL-2.0+
0002  *
0003  * Copyright (C) 2020 Renesas Electronics Corp.
0004  */
0005 #ifndef __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__
0006 #define __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__
0007
0008 #include <dt-bindings/clock/renesas-cpg-mssr.h>
0009
0010 /* r8a7742 CPG Core Clocks */
0011 #define R8A7742_CLK_Z       0
0012 #define R8A7742_CLK_Z2      1
0013 #define R8A7742_CLK_ZG      2
0014 #define R8A7742_CLK_ZTR     3
0015 #define R8A7742_CLK_ZTRD2   4
0016 #define R8A7742_CLK_ZT      5
0017 #define R8A7742_CLK_ZX      6
0018 #define R8A7742_CLK_ZS      7
0019 #define R8A7742_CLK_HP      8
0020 #define R8A7742_CLK_B       9
0021 #define R8A7742_CLK_LB      10
0022 #define R8A7742_CLK_P       11
0023 #define R8A7742_CLK_CL      12
0024 #define R8A7742_CLK_M2      13
0025 #define R8A7742_CLK_ZB3     14
0026 #define R8A7742_CLK_ZB3D2   15
0027 #define R8A7742_CLK_DDR     16
0028 #define R8A7742_CLK_SDH     17
0029 #define R8A7742_CLK_SD0     18
0030 #define R8A7742_CLK_SD1     19
0031 #define R8A7742_CLK_SD2     20
0032 #define R8A7742_CLK_SD3     21
0033 #define R8A7742_CLK_MMC0    22
0034 #define R8A7742_CLK_MMC1    23
0035 #define R8A7742_CLK_MP      24
0036 #define R8A7742_CLK_QSPI    25
0037 #define R8A7742_CLK_CP      26
0038 #define R8A7742_CLK_RCAN    27
0039 #define R8A7742_CLK_R       28
0040 #define R8A7742_CLK_OSC     29
0041
0042 #endif /* __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__ */