OSCL-LXR linux-6.0.1/​include/​dt-bindings/​clock/​qcom,gcc-qcm2290.h	Source navigation Diff markup Identifier search General search
	Version: linux-6.0.1 spark-3.0.0 hadoop-3.2.0-src hadoop-3.3.0-src spark-2.4.7 linux-4.15.13 hadoop-2.7.4-src Revert   Change

 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
 /*
  * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
  */
 
 #ifndef _DT_BINDINGS_CLK_QCOM_GCC_QCM2290_H
 #define _DT_BINDINGS_CLK_QCOM_GCC_QCM2290_H
 
 /* GCC clocks */
 #define GPLL0                       0
 #define GPLL0_OUT_AUX2                  1
 #define GPLL1                       2
 #define GPLL10                      3
 #define GPLL11                      4
 #define GPLL3                       5
 #define GPLL3_OUT_MAIN                  6
 #define GPLL4                       7
 #define GPLL5                       8
 #define GPLL6                       9
 #define GPLL6_OUT_MAIN                  10
 #define GPLL7                       11
 #define GPLL8                       12
 #define GPLL8_OUT_MAIN                  13
 #define GPLL9                       14
 #define GPLL9_OUT_MAIN                  15
 #define GCC_AHB2PHY_CSI_CLK             16
 #define GCC_AHB2PHY_USB_CLK             17
 #define GCC_APC_VS_CLK                  18
 #define GCC_BIMC_GPU_AXI_CLK                19
 #define GCC_BOOT_ROM_AHB_CLK                20
 #define GCC_CAM_THROTTLE_NRT_CLK            21
 #define GCC_CAM_THROTTLE_RT_CLK             22
 #define GCC_CAMERA_AHB_CLK              23
 #define GCC_CAMERA_XO_CLK               24
 #define GCC_CAMSS_AXI_CLK               25
 #define GCC_CAMSS_AXI_CLK_SRC               26
 #define GCC_CAMSS_CAMNOC_ATB_CLK            27
 #define GCC_CAMSS_CAMNOC_NTS_XO_CLK         28
 #define GCC_CAMSS_CCI_0_CLK             29
 #define GCC_CAMSS_CCI_CLK_SRC               30
 #define GCC_CAMSS_CPHY_0_CLK                31
 #define GCC_CAMSS_CPHY_1_CLK                32
 #define GCC_CAMSS_CSI0PHYTIMER_CLK          33
 #define GCC_CAMSS_CSI0PHYTIMER_CLK_SRC          34
 #define GCC_CAMSS_CSI1PHYTIMER_CLK          35
 #define GCC_CAMSS_CSI1PHYTIMER_CLK_SRC          36
 #define GCC_CAMSS_MCLK0_CLK             37
 #define GCC_CAMSS_MCLK0_CLK_SRC             38
 #define GCC_CAMSS_MCLK1_CLK             39
 #define GCC_CAMSS_MCLK1_CLK_SRC             40
 #define GCC_CAMSS_MCLK2_CLK             41
 #define GCC_CAMSS_MCLK2_CLK_SRC             42
 #define GCC_CAMSS_MCLK3_CLK             43
 #define GCC_CAMSS_MCLK3_CLK_SRC             44
 #define GCC_CAMSS_NRT_AXI_CLK               45
 #define GCC_CAMSS_OPE_AHB_CLK               46
 #define GCC_CAMSS_OPE_AHB_CLK_SRC           47
 #define GCC_CAMSS_OPE_CLK               48
 #define GCC_CAMSS_OPE_CLK_SRC               49
 #define GCC_CAMSS_RT_AXI_CLK                50
 #define GCC_CAMSS_TFE_0_CLK             51
 #define GCC_CAMSS_TFE_0_CLK_SRC             52
 #define GCC_CAMSS_TFE_0_CPHY_RX_CLK         53
 #define GCC_CAMSS_TFE_0_CSID_CLK            54
 #define GCC_CAMSS_TFE_0_CSID_CLK_SRC            55
 #define GCC_CAMSS_TFE_1_CLK             56
 #define GCC_CAMSS_TFE_1_CLK_SRC             57
 #define GCC_CAMSS_TFE_1_CPHY_RX_CLK         58
 #define GCC_CAMSS_TFE_1_CSID_CLK            59
 #define GCC_CAMSS_TFE_1_CSID_CLK_SRC            60
 #define GCC_CAMSS_TFE_CPHY_RX_CLK_SRC           61
 #define GCC_CAMSS_TOP_AHB_CLK               62
 #define GCC_CAMSS_TOP_AHB_CLK_SRC           63
 #define GCC_CFG_NOC_USB3_PRIM_AXI_CLK           64
 #define GCC_CPUSS_AHB_CLK               65
 #define GCC_CPUSS_AHB_CLK_SRC               66
 #define GCC_CPUSS_AHB_POSTDIV_CLK_SRC           67
 #define GCC_CPUSS_GNOC_CLK              68
 #define GCC_CPUSS_THROTTLE_CORE_CLK         69
 #define GCC_CPUSS_THROTTLE_XO_CLK           70
 #define GCC_DISP_AHB_CLK                71
 #define GCC_DISP_GPLL0_CLK_SRC              72
 #define GCC_DISP_GPLL0_DIV_CLK_SRC          73
 #define GCC_DISP_HF_AXI_CLK             74
 #define GCC_DISP_THROTTLE_CORE_CLK          75
 #define GCC_DISP_XO_CLK                 76
 #define GCC_GP1_CLK                 77
 #define GCC_GP1_CLK_SRC                 78
 #define GCC_GP2_CLK                 79
 #define GCC_GP2_CLK_SRC                 80
 #define GCC_GP3_CLK                 81
 #define GCC_GP3_CLK_SRC                 82
 #define GCC_GPU_CFG_AHB_CLK             83
 #define GCC_GPU_GPLL0_CLK_SRC               84
 #define GCC_GPU_GPLL0_DIV_CLK_SRC           85
 #define GCC_GPU_IREF_CLK                86
 #define GCC_GPU_MEMNOC_GFX_CLK              87
 #define GCC_GPU_SNOC_DVM_GFX_CLK            88
 #define GCC_GPU_THROTTLE_CORE_CLK           89
 #define GCC_GPU_THROTTLE_XO_CLK             90
 #define GCC_PDM2_CLK                    91
 #define GCC_PDM2_CLK_SRC                92
 #define GCC_PDM_AHB_CLK                 93
 #define GCC_PDM_XO4_CLK                 94
 #define GCC_PWM0_XO512_CLK              95
 #define GCC_QMIP_CAMERA_NRT_AHB_CLK         96
 #define GCC_QMIP_CAMERA_RT_AHB_CLK          97
 #define GCC_QMIP_CPUSS_CFG_AHB_CLK          98
 #define GCC_QMIP_DISP_AHB_CLK               99
 #define GCC_QMIP_GPU_CFG_AHB_CLK            100
 #define GCC_QMIP_VIDEO_VCODEC_AHB_CLK           101
 #define GCC_QUPV3_WRAP0_CORE_2X_CLK         102
 #define GCC_QUPV3_WRAP0_CORE_CLK            103
 #define GCC_QUPV3_WRAP0_S0_CLK              104
 #define GCC_QUPV3_WRAP0_S0_CLK_SRC          105
 #define GCC_QUPV3_WRAP0_S1_CLK              106
 #define GCC_QUPV3_WRAP0_S1_CLK_SRC          107
 #define GCC_QUPV3_WRAP0_S2_CLK              108
 #define GCC_QUPV3_WRAP0_S2_CLK_SRC          109
 #define GCC_QUPV3_WRAP0_S3_CLK              110
 #define GCC_QUPV3_WRAP0_S3_CLK_SRC          111
 #define GCC_QUPV3_WRAP0_S4_CLK              112
 #define GCC_QUPV3_WRAP0_S4_CLK_SRC          113
 #define GCC_QUPV3_WRAP0_S5_CLK              114
 #define GCC_QUPV3_WRAP0_S5_CLK_SRC          115
 #define GCC_QUPV3_WRAP_0_M_AHB_CLK          116
 #define GCC_QUPV3_WRAP_0_S_AHB_CLK          117
 #define GCC_SDCC1_AHB_CLK               118
 #define GCC_SDCC1_APPS_CLK              119
 #define GCC_SDCC1_APPS_CLK_SRC              120
 #define GCC_SDCC1_ICE_CORE_CLK              121
 #define GCC_SDCC1_ICE_CORE_CLK_SRC          122
 #define GCC_SDCC2_AHB_CLK               123
 #define GCC_SDCC2_APPS_CLK              124
 #define GCC_SDCC2_APPS_CLK_SRC              125
 #define GCC_SYS_NOC_CPUSS_AHB_CLK           126
 #define GCC_SYS_NOC_USB3_PRIM_AXI_CLK           127
 #define GCC_USB30_PRIM_MASTER_CLK           128
 #define GCC_USB30_PRIM_MASTER_CLK_SRC           129
 #define GCC_USB30_PRIM_MOCK_UTMI_CLK            130
 #define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC        131
 #define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV        132
 #define GCC_USB30_PRIM_SLEEP_CLK            133
 #define GCC_USB3_PRIM_CLKREF_CLK            134
 #define GCC_USB3_PRIM_PHY_AUX_CLK_SRC           135
 #define GCC_USB3_PRIM_PHY_COM_AUX_CLK           136
 #define GCC_USB3_PRIM_PHY_PIPE_CLK          137
 #define GCC_VCODEC0_AXI_CLK             138
 #define GCC_VENUS_AHB_CLK               139
 #define GCC_VENUS_CTL_AXI_CLK               140
 #define GCC_VIDEO_AHB_CLK               141
 #define GCC_VIDEO_AXI0_CLK              142
 #define GCC_VIDEO_THROTTLE_CORE_CLK         143
 #define GCC_VIDEO_VCODEC0_SYS_CLK           144
 #define GCC_VIDEO_VENUS_CLK_SRC             145
 #define GCC_VIDEO_VENUS_CTL_CLK             146
 #define GCC_VIDEO_XO_CLK                147
 
 /* GCC resets */
 #define GCC_CAMSS_OPE_BCR               0
 #define GCC_CAMSS_TFE_BCR               1
 #define GCC_CAMSS_TOP_BCR               2
 #define GCC_GPU_BCR                 3
 #define GCC_MMSS_BCR                    4
 #define GCC_PDM_BCR                 5
 #define GCC_QUPV3_WRAPPER_0_BCR             6
 #define GCC_SDCC1_BCR                   7
 #define GCC_SDCC2_BCR                   8
 #define GCC_USB30_PRIM_BCR              9
 #define GCC_USB_PHY_CFG_AHB2PHY_BCR         10
 #define GCC_VCODEC0_BCR                 11
 #define GCC_VENUS_BCR                   12
 #define GCC_VIDEO_INTERFACE_BCR             13
 #define GCC_QUSB2PHY_PRIM_BCR               14
 #define GCC_USB3_PHY_PRIM_SP0_BCR           15
 #define GCC_USB3PHY_PHY_PRIM_SP0_BCR            16
 
 /* Indexes for GDSCs */
 #define GCC_CAMSS_TOP_GDSC              0
 #define GCC_USB30_PRIM_GDSC             1
 #define GCC_VCODEC0_GDSC                2
 #define GCC_VENUS_GDSC                  3
 #define HLOS1_VOTE_TURING_MMU_TBU1_GDSC         4
 #define HLOS1_VOTE_TURING_MMU_TBU0_GDSC         5
 #define HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC      6
 #define HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC     7
 
 #endif

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