0001
0002
0003
0004
0005
0006 #ifndef _DT_BINDINGS_CLK_MSM_GCC_8960_H
0007 #define _DT_BINDINGS_CLK_MSM_GCC_8960_H
0008
0009 #define AFAB_CLK_SRC 0
0010 #define AFAB_CORE_CLK 1
0011 #define SFAB_MSS_Q6_SW_A_CLK 2
0012 #define SFAB_MSS_Q6_FW_A_CLK 3
0013 #define QDSS_STM_CLK 4
0014 #define SCSS_A_CLK 5
0015 #define SCSS_H_CLK 6
0016 #define SCSS_XO_SRC_CLK 7
0017 #define AFAB_EBI1_CH0_A_CLK 8
0018 #define AFAB_EBI1_CH1_A_CLK 9
0019 #define AFAB_AXI_S0_FCLK 10
0020 #define AFAB_AXI_S1_FCLK 11
0021 #define AFAB_AXI_S2_FCLK 12
0022 #define AFAB_AXI_S3_FCLK 13
0023 #define AFAB_AXI_S4_FCLK 14
0024 #define SFAB_CORE_CLK 15
0025 #define SFAB_AXI_S0_FCLK 16
0026 #define SFAB_AXI_S1_FCLK 17
0027 #define SFAB_AXI_S2_FCLK 18
0028 #define SFAB_AXI_S3_FCLK 19
0029 #define SFAB_AXI_S4_FCLK 20
0030 #define SFAB_AHB_S0_FCLK 21
0031 #define SFAB_AHB_S1_FCLK 22
0032 #define SFAB_AHB_S2_FCLK 23
0033 #define SFAB_AHB_S3_FCLK 24
0034 #define SFAB_AHB_S4_FCLK 25
0035 #define SFAB_AHB_S5_FCLK 26
0036 #define SFAB_AHB_S6_FCLK 27
0037 #define SFAB_AHB_S7_FCLK 28
0038 #define QDSS_AT_CLK_SRC 29
0039 #define QDSS_AT_CLK 30
0040 #define QDSS_TRACECLKIN_CLK_SRC 31
0041 #define QDSS_TRACECLKIN_CLK 32
0042 #define QDSS_TSCTR_CLK_SRC 33
0043 #define QDSS_TSCTR_CLK 34
0044 #define SFAB_ADM0_M0_A_CLK 35
0045 #define SFAB_ADM0_M1_A_CLK 36
0046 #define SFAB_ADM0_M2_H_CLK 37
0047 #define ADM0_CLK 38
0048 #define ADM0_PBUS_CLK 39
0049 #define MSS_XPU_CLK 40
0050 #define IMEM0_A_CLK 41
0051 #define QDSS_H_CLK 42
0052 #define PCIE_A_CLK 43
0053 #define PCIE_AUX_CLK 44
0054 #define PCIE_PHY_REF_CLK 45
0055 #define PCIE_H_CLK 46
0056 #define SFAB_CLK_SRC 47
0057 #define MAHB0_CLK 48
0058 #define Q6SW_CLK_SRC 49
0059 #define Q6SW_CLK 50
0060 #define Q6FW_CLK_SRC 51
0061 #define Q6FW_CLK 52
0062 #define SFAB_MSS_M_A_CLK 53
0063 #define SFAB_USB3_M_A_CLK 54
0064 #define SFAB_LPASS_Q6_A_CLK 55
0065 #define SFAB_AFAB_M_A_CLK 56
0066 #define AFAB_SFAB_M0_A_CLK 57
0067 #define AFAB_SFAB_M1_A_CLK 58
0068 #define SFAB_SATA_S_H_CLK 59
0069 #define DFAB_CLK_SRC 60
0070 #define DFAB_CLK 61
0071 #define SFAB_DFAB_M_A_CLK 62
0072 #define DFAB_SFAB_M_A_CLK 63
0073 #define DFAB_SWAY0_H_CLK 64
0074 #define DFAB_SWAY1_H_CLK 65
0075 #define DFAB_ARB0_H_CLK 66
0076 #define DFAB_ARB1_H_CLK 67
0077 #define PPSS_H_CLK 68
0078 #define PPSS_PROC_CLK 69
0079 #define PPSS_TIMER0_CLK 70
0080 #define PPSS_TIMER1_CLK 71
0081 #define PMEM_A_CLK 72
0082 #define DMA_BAM_H_CLK 73
0083 #define SIC_H_CLK 74
0084 #define SPS_TIC_H_CLK 75
0085 #define SLIMBUS_H_CLK 76
0086 #define SLIMBUS_XO_SRC_CLK 77
0087 #define CFPB_2X_CLK_SRC 78
0088 #define CFPB_CLK 79
0089 #define CFPB0_H_CLK 80
0090 #define CFPB1_H_CLK 81
0091 #define CFPB2_H_CLK 82
0092 #define SFAB_CFPB_M_H_CLK 83
0093 #define CFPB_MASTER_H_CLK 84
0094 #define SFAB_CFPB_S_H_CLK 85
0095 #define CFPB_SPLITTER_H_CLK 86
0096 #define TSIF_H_CLK 87
0097 #define TSIF_INACTIVITY_TIMERS_CLK 88
0098 #define TSIF_REF_SRC 89
0099 #define TSIF_REF_CLK 90
0100 #define CE1_H_CLK 91
0101 #define CE1_CORE_CLK 92
0102 #define CE1_SLEEP_CLK 93
0103 #define CE2_H_CLK 94
0104 #define CE2_CORE_CLK 95
0105 #define SFPB_H_CLK_SRC 97
0106 #define SFPB_H_CLK 98
0107 #define SFAB_SFPB_M_H_CLK 99
0108 #define SFAB_SFPB_S_H_CLK 100
0109 #define RPM_PROC_CLK 101
0110 #define RPM_BUS_H_CLK 102
0111 #define RPM_SLEEP_CLK 103
0112 #define RPM_TIMER_CLK 104
0113 #define RPM_MSG_RAM_H_CLK 105
0114 #define PMIC_ARB0_H_CLK 106
0115 #define PMIC_ARB1_H_CLK 107
0116 #define PMIC_SSBI2_SRC 108
0117 #define PMIC_SSBI2_CLK 109
0118 #define SDC1_H_CLK 110
0119 #define SDC2_H_CLK 111
0120 #define SDC3_H_CLK 112
0121 #define SDC4_H_CLK 113
0122 #define SDC5_H_CLK 114
0123 #define SDC1_SRC 115
0124 #define SDC2_SRC 116
0125 #define SDC3_SRC 117
0126 #define SDC4_SRC 118
0127 #define SDC5_SRC 119
0128 #define SDC1_CLK 120
0129 #define SDC2_CLK 121
0130 #define SDC3_CLK 122
0131 #define SDC4_CLK 123
0132 #define SDC5_CLK 124
0133 #define DFAB_A2_H_CLK 125
0134 #define USB_HS1_H_CLK 126
0135 #define USB_HS1_XCVR_SRC 127
0136 #define USB_HS1_XCVR_CLK 128
0137 #define USB_HSIC_H_CLK 129
0138 #define USB_HSIC_XCVR_FS_SRC 130
0139 #define USB_HSIC_XCVR_FS_CLK 131
0140 #define USB_HSIC_SYSTEM_CLK_SRC 132
0141 #define USB_HSIC_SYSTEM_CLK 133
0142 #define CFPB0_C0_H_CLK 134
0143 #define CFPB0_C1_H_CLK 135
0144 #define CFPB0_D0_H_CLK 136
0145 #define CFPB0_D1_H_CLK 137
0146 #define USB_FS1_H_CLK 138
0147 #define USB_FS1_XCVR_FS_SRC 139
0148 #define USB_FS1_XCVR_FS_CLK 140
0149 #define USB_FS1_SYSTEM_CLK 141
0150 #define USB_FS2_H_CLK 142
0151 #define USB_FS2_XCVR_FS_SRC 143
0152 #define USB_FS2_XCVR_FS_CLK 144
0153 #define USB_FS2_SYSTEM_CLK 145
0154 #define GSBI_COMMON_SIM_SRC 146
0155 #define GSBI1_H_CLK 147
0156 #define GSBI2_H_CLK 148
0157 #define GSBI3_H_CLK 149
0158 #define GSBI4_H_CLK 150
0159 #define GSBI5_H_CLK 151
0160 #define GSBI6_H_CLK 152
0161 #define GSBI7_H_CLK 153
0162 #define GSBI8_H_CLK 154
0163 #define GSBI9_H_CLK 155
0164 #define GSBI10_H_CLK 156
0165 #define GSBI11_H_CLK 157
0166 #define GSBI12_H_CLK 158
0167 #define GSBI1_UART_SRC 159
0168 #define GSBI1_UART_CLK 160
0169 #define GSBI2_UART_SRC 161
0170 #define GSBI2_UART_CLK 162
0171 #define GSBI3_UART_SRC 163
0172 #define GSBI3_UART_CLK 164
0173 #define GSBI4_UART_SRC 165
0174 #define GSBI4_UART_CLK 166
0175 #define GSBI5_UART_SRC 167
0176 #define GSBI5_UART_CLK 168
0177 #define GSBI6_UART_SRC 169
0178 #define GSBI6_UART_CLK 170
0179 #define GSBI7_UART_SRC 171
0180 #define GSBI7_UART_CLK 172
0181 #define GSBI8_UART_SRC 173
0182 #define GSBI8_UART_CLK 174
0183 #define GSBI9_UART_SRC 175
0184 #define GSBI9_UART_CLK 176
0185 #define GSBI10_UART_SRC 177
0186 #define GSBI10_UART_CLK 178
0187 #define GSBI11_UART_SRC 179
0188 #define GSBI11_UART_CLK 180
0189 #define GSBI12_UART_SRC 181
0190 #define GSBI12_UART_CLK 182
0191 #define GSBI1_QUP_SRC 183
0192 #define GSBI1_QUP_CLK 184
0193 #define GSBI2_QUP_SRC 185
0194 #define GSBI2_QUP_CLK 186
0195 #define GSBI3_QUP_SRC 187
0196 #define GSBI3_QUP_CLK 188
0197 #define GSBI4_QUP_SRC 189
0198 #define GSBI4_QUP_CLK 190
0199 #define GSBI5_QUP_SRC 191
0200 #define GSBI5_QUP_CLK 192
0201 #define GSBI6_QUP_SRC 193
0202 #define GSBI6_QUP_CLK 194
0203 #define GSBI7_QUP_SRC 195
0204 #define GSBI7_QUP_CLK 196
0205 #define GSBI8_QUP_SRC 197
0206 #define GSBI8_QUP_CLK 198
0207 #define GSBI9_QUP_SRC 199
0208 #define GSBI9_QUP_CLK 200
0209 #define GSBI10_QUP_SRC 201
0210 #define GSBI10_QUP_CLK 202
0211 #define GSBI11_QUP_SRC 203
0212 #define GSBI11_QUP_CLK 204
0213 #define GSBI12_QUP_SRC 205
0214 #define GSBI12_QUP_CLK 206
0215 #define GSBI1_SIM_CLK 207
0216 #define GSBI2_SIM_CLK 208
0217 #define GSBI3_SIM_CLK 209
0218 #define GSBI4_SIM_CLK 210
0219 #define GSBI5_SIM_CLK 211
0220 #define GSBI6_SIM_CLK 212
0221 #define GSBI7_SIM_CLK 213
0222 #define GSBI8_SIM_CLK 214
0223 #define GSBI9_SIM_CLK 215
0224 #define GSBI10_SIM_CLK 216
0225 #define GSBI11_SIM_CLK 217
0226 #define GSBI12_SIM_CLK 218
0227 #define USB_HSIC_HSIC_CLK_SRC 219
0228 #define USB_HSIC_HSIC_CLK 220
0229 #define USB_HSIC_HSIO_CAL_CLK 221
0230 #define SPDM_CFG_H_CLK 222
0231 #define SPDM_MSTR_H_CLK 223
0232 #define SPDM_FF_CLK_SRC 224
0233 #define SPDM_FF_CLK 225
0234 #define SEC_CTRL_CLK 226
0235 #define SEC_CTRL_ACC_CLK_SRC 227
0236 #define SEC_CTRL_ACC_CLK 228
0237 #define TLMM_H_CLK 229
0238 #define TLMM_CLK 230
0239 #define SFAB_MSS_S_H_CLK 231
0240 #define MSS_SLP_CLK 232
0241 #define MSS_Q6SW_JTAG_CLK 233
0242 #define MSS_Q6FW_JTAG_CLK 234
0243 #define MSS_S_H_CLK 235
0244 #define MSS_CXO_SRC_CLK 236
0245 #define SATA_H_CLK 237
0246 #define SATA_CLK_SRC 238
0247 #define SATA_RXOOB_CLK 239
0248 #define SATA_PMALIVE_CLK 240
0249 #define SATA_PHY_REF_CLK 241
0250 #define TSSC_CLK_SRC 242
0251 #define TSSC_CLK 243
0252 #define PDM_SRC 244
0253 #define PDM_CLK 245
0254 #define GP0_SRC 246
0255 #define GP0_CLK 247
0256 #define GP1_SRC 248
0257 #define GP1_CLK 249
0258 #define GP2_SRC 250
0259 #define GP2_CLK 251
0260 #define MPM_CLK 252
0261 #define EBI1_CLK_SRC 253
0262 #define EBI1_CH0_CLK 254
0263 #define EBI1_CH1_CLK 255
0264 #define EBI1_2X_CLK 256
0265 #define EBI1_CH0_DQ_CLK 257
0266 #define EBI1_CH1_DQ_CLK 258
0267 #define EBI1_CH0_CA_CLK 259
0268 #define EBI1_CH1_CA_CLK 260
0269 #define EBI1_XO_CLK 261
0270 #define SFAB_SMPSS_S_H_CLK 262
0271 #define PRNG_SRC 263
0272 #define PRNG_CLK 264
0273 #define PXO_SRC 265
0274 #define LPASS_CXO_CLK 266
0275 #define LPASS_PXO_CLK 267
0276 #define SPDM_CY_PORT0_CLK 268
0277 #define SPDM_CY_PORT1_CLK 269
0278 #define SPDM_CY_PORT2_CLK 270
0279 #define SPDM_CY_PORT3_CLK 271
0280 #define SPDM_CY_PORT4_CLK 272
0281 #define SPDM_CY_PORT5_CLK 273
0282 #define SPDM_CY_PORT6_CLK 274
0283 #define SPDM_CY_PORT7_CLK 275
0284 #define PLL0 276
0285 #define PLL0_VOTE 277
0286 #define PLL3 278
0287 #define PLL3_VOTE 279
0288 #define PLL4_VOTE 280
0289 #define PLL5 281
0290 #define PLL5_VOTE 282
0291 #define PLL6 283
0292 #define PLL6_VOTE 284
0293 #define PLL7_VOTE 285
0294 #define PLL8 286
0295 #define PLL8_VOTE 287
0296 #define PLL9 288
0297 #define PLL10 289
0298 #define PLL11 290
0299 #define PLL12 291
0300 #define PLL13 292
0301 #define PLL14 293
0302 #define PLL14_VOTE 294
0303 #define USB_HS3_H_CLK 295
0304 #define USB_HS3_XCVR_SRC 296
0305 #define USB_HS3_XCVR_CLK 297
0306 #define USB_HS4_H_CLK 298
0307 #define USB_HS4_XCVR_SRC 299
0308 #define USB_HS4_XCVR_CLK 300
0309 #define SATA_PHY_CFG_CLK 301
0310 #define SATA_A_CLK 302
0311 #define CE3_SRC 303
0312 #define CE3_CORE_CLK 304
0313 #define CE3_H_CLK 305
0314 #define PLL16 306
0315 #define PLL17 307
0316
0317 #endif