dt-bindings/clock/qcom%2Cdispcc-sm8250.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
0004  */
0005
0006 #ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8250_H
0007 #define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8250_H
0008
0009 /* DISP_CC clock registers */
0010 #define DISP_CC_MDSS_AHB_CLK            0
0011 #define DISP_CC_MDSS_AHB_CLK_SRC        1
0012 #define DISP_CC_MDSS_BYTE0_CLK          2
0013 #define DISP_CC_MDSS_BYTE0_CLK_SRC      3
0014 #define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC      4
0015 #define DISP_CC_MDSS_BYTE0_INTF_CLK     5
0016 #define DISP_CC_MDSS_BYTE1_CLK          6
0017 #define DISP_CC_MDSS_BYTE1_CLK_SRC      7
0018 #define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC      8
0019 #define DISP_CC_MDSS_BYTE1_INTF_CLK     9
0020 #define DISP_CC_MDSS_DP_AUX1_CLK        10
0021 #define DISP_CC_MDSS_DP_AUX1_CLK_SRC        11
0022 #define DISP_CC_MDSS_DP_AUX_CLK         12
0023 #define DISP_CC_MDSS_DP_AUX_CLK_SRC     13
0024 #define DISP_CC_MDSS_DP_LINK1_CLK       14
0025 #define DISP_CC_MDSS_DP_LINK1_CLK_SRC       15
0026 #define DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC   16
0027 #define DISP_CC_MDSS_DP_LINK1_INTF_CLK      17
0028 #define DISP_CC_MDSS_DP_LINK_CLK        18
0029 #define DISP_CC_MDSS_DP_LINK_CLK_SRC        19
0030 #define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC    20
0031 #define DISP_CC_MDSS_DP_LINK_INTF_CLK       21
0032 #define DISP_CC_MDSS_DP_PIXEL1_CLK      22
0033 #define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC      23
0034 #define DISP_CC_MDSS_DP_PIXEL2_CLK      24
0035 #define DISP_CC_MDSS_DP_PIXEL2_CLK_SRC      25
0036 #define DISP_CC_MDSS_DP_PIXEL_CLK       26
0037 #define DISP_CC_MDSS_DP_PIXEL_CLK_SRC       27
0038 #define DISP_CC_MDSS_ESC0_CLK           28
0039 #define DISP_CC_MDSS_ESC0_CLK_SRC       29
0040 #define DISP_CC_MDSS_ESC1_CLK           30
0041 #define DISP_CC_MDSS_ESC1_CLK_SRC       31
0042 #define DISP_CC_MDSS_MDP_CLK            32
0043 #define DISP_CC_MDSS_MDP_CLK_SRC        33
0044 #define DISP_CC_MDSS_MDP_LUT_CLK        34
0045 #define DISP_CC_MDSS_NON_GDSC_AHB_CLK       35
0046 #define DISP_CC_MDSS_PCLK0_CLK          36
0047 #define DISP_CC_MDSS_PCLK0_CLK_SRC      37
0048 #define DISP_CC_MDSS_PCLK1_CLK          38
0049 #define DISP_CC_MDSS_PCLK1_CLK_SRC      39
0050 #define DISP_CC_MDSS_ROT_CLK            40
0051 #define DISP_CC_MDSS_ROT_CLK_SRC        41
0052 #define DISP_CC_MDSS_RSCC_AHB_CLK       42
0053 #define DISP_CC_MDSS_RSCC_VSYNC_CLK     43
0054 #define DISP_CC_MDSS_VSYNC_CLK          44
0055 #define DISP_CC_MDSS_VSYNC_CLK_SRC      45
0056 #define DISP_CC_PLL0                46
0057 #define DISP_CC_PLL1                47
0058 #define DISP_CC_MDSS_EDP_AUX_CLK        48
0059 #define DISP_CC_MDSS_EDP_AUX_CLK_SRC        49
0060 #define DISP_CC_MDSS_EDP_GTC_CLK        50
0061 #define DISP_CC_MDSS_EDP_GTC_CLK_SRC        51
0062 #define DISP_CC_MDSS_EDP_LINK_CLK       52
0063 #define DISP_CC_MDSS_EDP_LINK_CLK_SRC       53
0064 #define DISP_CC_MDSS_EDP_LINK_INTF_CLK      54
0065 #define DISP_CC_MDSS_EDP_PIXEL_CLK      55
0066 #define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC      56
0067
0068 /* DISP_CC Reset */
0069 #define DISP_CC_MDSS_CORE_BCR           0
0070 #define DISP_CC_MDSS_RSCC_BCR           1
0071
0072 /* DISP_CC GDSCR */
0073 #define MDSS_GDSC               0
0074
0075 #endif