dt-bindings/clock/qcom%2Cdispcc-sc7280.h

0001 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
0002 /*
0003  * Copyright (c) 2021, The Linux Foundation. All rights reserved.
0004  */
0005
0006 #ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7280_H
0007 #define _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7280_H
0008
0009 /* DISP_CC clocks */
0010 #define DISP_CC_PLL0                    0
0011 #define DISP_CC_MDSS_AHB_CLK                1
0012 #define DISP_CC_MDSS_AHB_CLK_SRC            2
0013 #define DISP_CC_MDSS_BYTE0_CLK              3
0014 #define DISP_CC_MDSS_BYTE0_CLK_SRC          4
0015 #define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC          5
0016 #define DISP_CC_MDSS_BYTE0_INTF_CLK         6
0017 #define DISP_CC_MDSS_DP_AUX_CLK             7
0018 #define DISP_CC_MDSS_DP_AUX_CLK_SRC         8
0019 #define DISP_CC_MDSS_DP_CRYPTO_CLK          9
0020 #define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC          10
0021 #define DISP_CC_MDSS_DP_LINK_CLK            11
0022 #define DISP_CC_MDSS_DP_LINK_CLK_SRC            12
0023 #define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC        13
0024 #define DISP_CC_MDSS_DP_LINK_INTF_CLK           14
0025 #define DISP_CC_MDSS_DP_PIXEL_CLK           15
0026 #define DISP_CC_MDSS_DP_PIXEL_CLK_SRC           16
0027 #define DISP_CC_MDSS_EDP_AUX_CLK            17
0028 #define DISP_CC_MDSS_EDP_AUX_CLK_SRC            18
0029 #define DISP_CC_MDSS_EDP_LINK_CLK           19
0030 #define DISP_CC_MDSS_EDP_LINK_CLK_SRC           20
0031 #define DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC       21
0032 #define DISP_CC_MDSS_EDP_LINK_INTF_CLK          22
0033 #define DISP_CC_MDSS_EDP_PIXEL_CLK          23
0034 #define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC          24
0035 #define DISP_CC_MDSS_ESC0_CLK               25
0036 #define DISP_CC_MDSS_ESC0_CLK_SRC           26
0037 #define DISP_CC_MDSS_MDP_CLK                27
0038 #define DISP_CC_MDSS_MDP_CLK_SRC            28
0039 #define DISP_CC_MDSS_MDP_LUT_CLK            29
0040 #define DISP_CC_MDSS_NON_GDSC_AHB_CLK           30
0041 #define DISP_CC_MDSS_PCLK0_CLK              31
0042 #define DISP_CC_MDSS_PCLK0_CLK_SRC          32
0043 #define DISP_CC_MDSS_ROT_CLK                33
0044 #define DISP_CC_MDSS_ROT_CLK_SRC            34
0045 #define DISP_CC_MDSS_RSCC_AHB_CLK           35
0046 #define DISP_CC_MDSS_RSCC_VSYNC_CLK         36
0047 #define DISP_CC_MDSS_VSYNC_CLK              37
0048 #define DISP_CC_MDSS_VSYNC_CLK_SRC          38
0049 #define DISP_CC_SLEEP_CLK               39
0050 #define DISP_CC_XO_CLK                  40
0051
0052 /* DISP_CC power domains */
0053 #define DISP_CC_MDSS_CORE_GDSC              0
0054
0055 #endif