dt-bindings/clock/qcom%2Ccamcc-sm8250.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
0004  */
0005
0006 #ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8250_H
0007 #define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8250_H
0008
0009 /* CAM_CC clocks */
0010 #define CAM_CC_BPS_AHB_CLK      0
0011 #define CAM_CC_BPS_AREG_CLK     1
0012 #define CAM_CC_BPS_AXI_CLK      2
0013 #define CAM_CC_BPS_CLK          3
0014 #define CAM_CC_BPS_CLK_SRC      4
0015 #define CAM_CC_CAMNOC_AXI_CLK       5
0016 #define CAM_CC_CAMNOC_AXI_CLK_SRC   6
0017 #define CAM_CC_CAMNOC_DCD_XO_CLK    7
0018 #define CAM_CC_CCI_0_CLK        8
0019 #define CAM_CC_CCI_0_CLK_SRC        9
0020 #define CAM_CC_CCI_1_CLK        10
0021 #define CAM_CC_CCI_1_CLK_SRC        11
0022 #define CAM_CC_CORE_AHB_CLK     12
0023 #define CAM_CC_CPAS_AHB_CLK     13
0024 #define CAM_CC_CPHY_RX_CLK_SRC      14
0025 #define CAM_CC_CSI0PHYTIMER_CLK     15
0026 #define CAM_CC_CSI0PHYTIMER_CLK_SRC 16
0027 #define CAM_CC_CSI1PHYTIMER_CLK     17
0028 #define CAM_CC_CSI1PHYTIMER_CLK_SRC 18
0029 #define CAM_CC_CSI2PHYTIMER_CLK     19
0030 #define CAM_CC_CSI2PHYTIMER_CLK_SRC 20
0031 #define CAM_CC_CSI3PHYTIMER_CLK     21
0032 #define CAM_CC_CSI3PHYTIMER_CLK_SRC 22
0033 #define CAM_CC_CSI4PHYTIMER_CLK     23
0034 #define CAM_CC_CSI4PHYTIMER_CLK_SRC 24
0035 #define CAM_CC_CSI5PHYTIMER_CLK     25
0036 #define CAM_CC_CSI5PHYTIMER_CLK_SRC 26
0037 #define CAM_CC_CSIPHY0_CLK      27
0038 #define CAM_CC_CSIPHY1_CLK      28
0039 #define CAM_CC_CSIPHY2_CLK      29
0040 #define CAM_CC_CSIPHY3_CLK      30
0041 #define CAM_CC_CSIPHY4_CLK      31
0042 #define CAM_CC_CSIPHY5_CLK      32
0043 #define CAM_CC_FAST_AHB_CLK_SRC     33
0044 #define CAM_CC_FD_CORE_CLK      34
0045 #define CAM_CC_FD_CORE_CLK_SRC      35
0046 #define CAM_CC_FD_CORE_UAR_CLK      36
0047 #define CAM_CC_GDSC_CLK         37
0048 #define CAM_CC_ICP_AHB_CLK      38
0049 #define CAM_CC_ICP_CLK          39
0050 #define CAM_CC_ICP_CLK_SRC      40
0051 #define CAM_CC_IFE_0_AHB_CLK        41
0052 #define CAM_CC_IFE_0_AREG_CLK       42
0053 #define CAM_CC_IFE_0_AXI_CLK        43
0054 #define CAM_CC_IFE_0_CLK        44
0055 #define CAM_CC_IFE_0_CLK_SRC        45
0056 #define CAM_CC_IFE_0_CPHY_RX_CLK    46
0057 #define CAM_CC_IFE_0_CSID_CLK       47
0058 #define CAM_CC_IFE_0_CSID_CLK_SRC   48
0059 #define CAM_CC_IFE_0_DSP_CLK        49
0060 #define CAM_CC_IFE_1_AHB_CLK        50
0061 #define CAM_CC_IFE_1_AREG_CLK       51
0062 #define CAM_CC_IFE_1_AXI_CLK        52
0063 #define CAM_CC_IFE_1_CLK        53
0064 #define CAM_CC_IFE_1_CLK_SRC        54
0065 #define CAM_CC_IFE_1_CPHY_RX_CLK    55
0066 #define CAM_CC_IFE_1_CSID_CLK       56
0067 #define CAM_CC_IFE_1_CSID_CLK_SRC   57
0068 #define CAM_CC_IFE_1_DSP_CLK        58
0069 #define CAM_CC_IFE_LITE_AHB_CLK     59
0070 #define CAM_CC_IFE_LITE_AXI_CLK     60
0071 #define CAM_CC_IFE_LITE_CLK     61
0072 #define CAM_CC_IFE_LITE_CLK_SRC     62
0073 #define CAM_CC_IFE_LITE_CPHY_RX_CLK 63
0074 #define CAM_CC_IFE_LITE_CSID_CLK    64
0075 #define CAM_CC_IFE_LITE_CSID_CLK_SRC    65
0076 #define CAM_CC_IPE_0_AHB_CLK        66
0077 #define CAM_CC_IPE_0_AREG_CLK       67
0078 #define CAM_CC_IPE_0_AXI_CLK        68
0079 #define CAM_CC_IPE_0_CLK        69
0080 #define CAM_CC_IPE_0_CLK_SRC        70
0081 #define CAM_CC_JPEG_CLK         71
0082 #define CAM_CC_JPEG_CLK_SRC     72
0083 #define CAM_CC_MCLK0_CLK        73
0084 #define CAM_CC_MCLK0_CLK_SRC        74
0085 #define CAM_CC_MCLK1_CLK        75
0086 #define CAM_CC_MCLK1_CLK_SRC        76
0087 #define CAM_CC_MCLK2_CLK        77
0088 #define CAM_CC_MCLK2_CLK_SRC        78
0089 #define CAM_CC_MCLK3_CLK        79
0090 #define CAM_CC_MCLK3_CLK_SRC        80
0091 #define CAM_CC_MCLK4_CLK        81
0092 #define CAM_CC_MCLK4_CLK_SRC        82
0093 #define CAM_CC_MCLK5_CLK        83
0094 #define CAM_CC_MCLK5_CLK_SRC        84
0095 #define CAM_CC_MCLK6_CLK        85
0096 #define CAM_CC_MCLK6_CLK_SRC        86
0097 #define CAM_CC_PLL0         87
0098 #define CAM_CC_PLL0_OUT_EVEN        88
0099 #define CAM_CC_PLL0_OUT_ODD     89
0100 #define CAM_CC_PLL1         90
0101 #define CAM_CC_PLL1_OUT_EVEN        91
0102 #define CAM_CC_PLL2         92
0103 #define CAM_CC_PLL2_OUT_MAIN        93
0104 #define CAM_CC_PLL3         94
0105 #define CAM_CC_PLL3_OUT_EVEN        95
0106 #define CAM_CC_PLL4         96
0107 #define CAM_CC_PLL4_OUT_EVEN        97
0108 #define CAM_CC_SBI_AHB_CLK      98
0109 #define CAM_CC_SBI_AXI_CLK      99
0110 #define CAM_CC_SBI_CLK          100
0111 #define CAM_CC_SBI_CPHY_RX_CLK      101
0112 #define CAM_CC_SBI_CSID_CLK     102
0113 #define CAM_CC_SBI_CSID_CLK_SRC     103
0114 #define CAM_CC_SBI_DIV_CLK_SRC      104
0115 #define CAM_CC_SBI_IFE_0_CLK        105
0116 #define CAM_CC_SBI_IFE_1_CLK        106
0117 #define CAM_CC_SLEEP_CLK        107
0118 #define CAM_CC_SLEEP_CLK_SRC        108
0119 #define CAM_CC_SLOW_AHB_CLK_SRC     109
0120 #define CAM_CC_XO_CLK_SRC       110
0121
0122 /* CAM_CC resets */
0123 #define CAM_CC_BPS_BCR          0
0124 #define CAM_CC_ICP_BCR          1
0125 #define CAM_CC_IFE_0_BCR        2
0126 #define CAM_CC_IFE_1_BCR        3
0127 #define CAM_CC_IPE_0_BCR        4
0128 #define CAM_CC_SBI_BCR          5
0129
0130 /* CAM_CC GDSCRs */
0131 #define BPS_GDSC            0
0132 #define IPE_0_GDSC          1
0133 #define SBI_GDSC            2
0134 #define IFE_0_GDSC          3
0135 #define IFE_1_GDSC          4
0136 #define TITAN_TOP_GDSC          5
0137
0138 #endif