dt-bindings/clock/qcom%2Ccamcc-sdm845.h

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
0004  */
0005
0006 #ifndef _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H
0007 #define _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H
0008
0009 /* CAM_CC clock registers */
0010 #define CAM_CC_BPS_AHB_CLK              0
0011 #define CAM_CC_BPS_AREG_CLK             1
0012 #define CAM_CC_BPS_AXI_CLK              2
0013 #define CAM_CC_BPS_CLK                  3
0014 #define CAM_CC_BPS_CLK_SRC              4
0015 #define CAM_CC_CAMNOC_ATB_CLK               5
0016 #define CAM_CC_CAMNOC_AXI_CLK               6
0017 #define CAM_CC_CCI_CLK                  7
0018 #define CAM_CC_CCI_CLK_SRC              8
0019 #define CAM_CC_CPAS_AHB_CLK             9
0020 #define CAM_CC_CPHY_RX_CLK_SRC              10
0021 #define CAM_CC_CSI0PHYTIMER_CLK             11
0022 #define CAM_CC_CSI0PHYTIMER_CLK_SRC         12
0023 #define CAM_CC_CSI1PHYTIMER_CLK             13
0024 #define CAM_CC_CSI1PHYTIMER_CLK_SRC         14
0025 #define CAM_CC_CSI2PHYTIMER_CLK             15
0026 #define CAM_CC_CSI2PHYTIMER_CLK_SRC         16
0027 #define CAM_CC_CSI3PHYTIMER_CLK             17
0028 #define CAM_CC_CSI3PHYTIMER_CLK_SRC         18
0029 #define CAM_CC_CSIPHY0_CLK              19
0030 #define CAM_CC_CSIPHY1_CLK              20
0031 #define CAM_CC_CSIPHY2_CLK              21
0032 #define CAM_CC_CSIPHY3_CLK              22
0033 #define CAM_CC_FAST_AHB_CLK_SRC             23
0034 #define CAM_CC_FD_CORE_CLK              24
0035 #define CAM_CC_FD_CORE_CLK_SRC              25
0036 #define CAM_CC_FD_CORE_UAR_CLK              26
0037 #define CAM_CC_ICP_APB_CLK              27
0038 #define CAM_CC_ICP_ATB_CLK              28
0039 #define CAM_CC_ICP_CLK                  29
0040 #define CAM_CC_ICP_CLK_SRC              30
0041 #define CAM_CC_ICP_CTI_CLK              31
0042 #define CAM_CC_ICP_TS_CLK               32
0043 #define CAM_CC_IFE_0_AXI_CLK                33
0044 #define CAM_CC_IFE_0_CLK                34
0045 #define CAM_CC_IFE_0_CLK_SRC                35
0046 #define CAM_CC_IFE_0_CPHY_RX_CLK            36
0047 #define CAM_CC_IFE_0_CSID_CLK               37
0048 #define CAM_CC_IFE_0_CSID_CLK_SRC           38
0049 #define CAM_CC_IFE_0_DSP_CLK                39
0050 #define CAM_CC_IFE_1_AXI_CLK                40
0051 #define CAM_CC_IFE_1_CLK                41
0052 #define CAM_CC_IFE_1_CLK_SRC                42
0053 #define CAM_CC_IFE_1_CPHY_RX_CLK            43
0054 #define CAM_CC_IFE_1_CSID_CLK               44
0055 #define CAM_CC_IFE_1_CSID_CLK_SRC           45
0056 #define CAM_CC_IFE_1_DSP_CLK                46
0057 #define CAM_CC_IFE_LITE_CLK             47
0058 #define CAM_CC_IFE_LITE_CLK_SRC             48
0059 #define CAM_CC_IFE_LITE_CPHY_RX_CLK         49
0060 #define CAM_CC_IFE_LITE_CSID_CLK            50
0061 #define CAM_CC_IFE_LITE_CSID_CLK_SRC            51
0062 #define CAM_CC_IPE_0_AHB_CLK                52
0063 #define CAM_CC_IPE_0_AREG_CLK               53
0064 #define CAM_CC_IPE_0_AXI_CLK                54
0065 #define CAM_CC_IPE_0_CLK                55
0066 #define CAM_CC_IPE_0_CLK_SRC                56
0067 #define CAM_CC_IPE_1_AHB_CLK                57
0068 #define CAM_CC_IPE_1_AREG_CLK               58
0069 #define CAM_CC_IPE_1_AXI_CLK                59
0070 #define CAM_CC_IPE_1_CLK                60
0071 #define CAM_CC_IPE_1_CLK_SRC                61
0072 #define CAM_CC_JPEG_CLK                 62
0073 #define CAM_CC_JPEG_CLK_SRC             63
0074 #define CAM_CC_LRME_CLK                 64
0075 #define CAM_CC_LRME_CLK_SRC             65
0076 #define CAM_CC_MCLK0_CLK                66
0077 #define CAM_CC_MCLK0_CLK_SRC                67
0078 #define CAM_CC_MCLK1_CLK                68
0079 #define CAM_CC_MCLK1_CLK_SRC                69
0080 #define CAM_CC_MCLK2_CLK                70
0081 #define CAM_CC_MCLK2_CLK_SRC                71
0082 #define CAM_CC_MCLK3_CLK                72
0083 #define CAM_CC_MCLK3_CLK_SRC                73
0084 #define CAM_CC_PLL0                 74
0085 #define CAM_CC_PLL0_OUT_EVEN                75
0086 #define CAM_CC_PLL1                 76
0087 #define CAM_CC_PLL1_OUT_EVEN                77
0088 #define CAM_CC_PLL2                 78
0089 #define CAM_CC_PLL2_OUT_EVEN                79
0090 #define CAM_CC_PLL3                 80
0091 #define CAM_CC_PLL3_OUT_EVEN                81
0092 #define CAM_CC_SLOW_AHB_CLK_SRC             82
0093 #define CAM_CC_SOC_AHB_CLK              83
0094 #define CAM_CC_SYS_TMR_CLK              84
0095
0096 /* CAM_CC Resets */
0097 #define TITAN_CAM_CC_CCI_BCR                0
0098 #define TITAN_CAM_CC_CPAS_BCR               1
0099 #define TITAN_CAM_CC_CSI0PHY_BCR            2
0100 #define TITAN_CAM_CC_CSI1PHY_BCR            3
0101 #define TITAN_CAM_CC_CSI2PHY_BCR            4
0102 #define TITAN_CAM_CC_MCLK0_BCR              5
0103 #define TITAN_CAM_CC_MCLK1_BCR              6
0104 #define TITAN_CAM_CC_MCLK2_BCR              7
0105 #define TITAN_CAM_CC_MCLK3_BCR              8
0106 #define TITAN_CAM_CC_TITAN_TOP_BCR          9
0107
0108 /* CAM_CC GDSCRs */
0109 #define BPS_GDSC                    0
0110 #define IPE_0_GDSC                  1
0111 #define IPE_1_GDSC                  2
0112 #define IFE_0_GDSC                  3
0113 #define IFE_1_GDSC                  4
0114 #define TITAN_TOP_GDSC                  5
0115
0116 #endif