dt-bindings/clock/omap4.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright 2017 Texas Instruments, Inc.
0004  */
0005 #ifndef __DT_BINDINGS_CLK_OMAP4_H
0006 #define __DT_BINDINGS_CLK_OMAP4_H
0007
0008 #define OMAP4_CLKCTRL_OFFSET    0x20
0009 #define OMAP4_CLKCTRL_INDEX(offset) ((offset) - OMAP4_CLKCTRL_OFFSET)
0010
0011 /* mpuss clocks */
0012 #define OMAP4_MPU_CLKCTRL   OMAP4_CLKCTRL_INDEX(0x20)
0013
0014 /* tesla clocks */
0015 #define OMAP4_DSP_CLKCTRL   OMAP4_CLKCTRL_INDEX(0x20)
0016
0017 /* abe clocks */
0018 #define OMAP4_L4_ABE_CLKCTRL    OMAP4_CLKCTRL_INDEX(0x20)
0019 #define OMAP4_AESS_CLKCTRL  OMAP4_CLKCTRL_INDEX(0x28)
0020 #define OMAP4_MCPDM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
0021 #define OMAP4_DMIC_CLKCTRL  OMAP4_CLKCTRL_INDEX(0x38)
0022 #define OMAP4_MCASP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40)
0023 #define OMAP4_MCBSP1_CLKCTRL    OMAP4_CLKCTRL_INDEX(0x48)
0024 #define OMAP4_MCBSP2_CLKCTRL    OMAP4_CLKCTRL_INDEX(0x50)
0025 #define OMAP4_MCBSP3_CLKCTRL    OMAP4_CLKCTRL_INDEX(0x58)
0026 #define OMAP4_SLIMBUS1_CLKCTRL  OMAP4_CLKCTRL_INDEX(0x60)
0027 #define OMAP4_TIMER5_CLKCTRL    OMAP4_CLKCTRL_INDEX(0x68)
0028 #define OMAP4_TIMER6_CLKCTRL    OMAP4_CLKCTRL_INDEX(0x70)
0029 #define OMAP4_TIMER7_CLKCTRL    OMAP4_CLKCTRL_INDEX(0x78)
0030 #define OMAP4_TIMER8_CLKCTRL    OMAP4_CLKCTRL_INDEX(0x80)
0031 #define OMAP4_WD_TIMER3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x88)
0032
0033 /* l4_ao clocks */
0034 #define OMAP4_SMARTREFLEX_MPU_CLKCTRL   OMAP4_CLKCTRL_INDEX(0x28)
0035 #define OMAP4_SMARTREFLEX_IVA_CLKCTRL   OMAP4_CLKCTRL_INDEX(0x30)
0036 #define OMAP4_SMARTREFLEX_CORE_CLKCTRL  OMAP4_CLKCTRL_INDEX(0x38)
0037
0038 /* l3_1 clocks */
0039 #define OMAP4_L3_MAIN_1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
0040
0041 /* l3_2 clocks */
0042 #define OMAP4_L3_MAIN_2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
0043 #define OMAP4_GPMC_CLKCTRL  OMAP4_CLKCTRL_INDEX(0x28)
0044 #define OMAP4_OCMC_RAM_CLKCTRL  OMAP4_CLKCTRL_INDEX(0x30)
0045
0046 /* ducati clocks */
0047 #define OMAP4_IPU_CLKCTRL   OMAP4_CLKCTRL_INDEX(0x20)
0048
0049 /* l3_dma clocks */
0050 #define OMAP4_DMA_SYSTEM_CLKCTRL    OMAP4_CLKCTRL_INDEX(0x20)
0051
0052 /* l3_emif clocks */
0053 #define OMAP4_DMM_CLKCTRL   OMAP4_CLKCTRL_INDEX(0x20)
0054 #define OMAP4_EMIF1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
0055 #define OMAP4_EMIF2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
0056
0057 /* d2d clocks */
0058 #define OMAP4_C2C_CLKCTRL   OMAP4_CLKCTRL_INDEX(0x20)
0059
0060 /* l4_cfg clocks */
0061 #define OMAP4_L4_CFG_CLKCTRL    OMAP4_CLKCTRL_INDEX(0x20)
0062 #define OMAP4_SPINLOCK_CLKCTRL  OMAP4_CLKCTRL_INDEX(0x28)
0063 #define OMAP4_MAILBOX_CLKCTRL   OMAP4_CLKCTRL_INDEX(0x30)
0064
0065 /* l3_instr clocks */
0066 #define OMAP4_L3_MAIN_3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
0067 #define OMAP4_L3_INSTR_CLKCTRL  OMAP4_CLKCTRL_INDEX(0x28)
0068 #define OMAP4_OCP_WP_NOC_CLKCTRL    OMAP4_CLKCTRL_INDEX(0x40)
0069
0070 /* ivahd clocks */
0071 #define OMAP4_IVA_CLKCTRL   OMAP4_CLKCTRL_INDEX(0x20)
0072 #define OMAP4_SL2IF_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
0073
0074 /* iss clocks */
0075 #define OMAP4_ISS_CLKCTRL   OMAP4_CLKCTRL_INDEX(0x20)
0076 #define OMAP4_FDIF_CLKCTRL  OMAP4_CLKCTRL_INDEX(0x28)
0077
0078 /* l3_dss clocks */
0079 #define OMAP4_DSS_CORE_CLKCTRL  OMAP4_CLKCTRL_INDEX(0x20)
0080
0081 /* l3_gfx clocks */
0082 #define OMAP4_GPU_CLKCTRL   OMAP4_CLKCTRL_INDEX(0x20)
0083
0084 /* l3_init clocks */
0085 #define OMAP4_MMC1_CLKCTRL  OMAP4_CLKCTRL_INDEX(0x28)
0086 #define OMAP4_MMC2_CLKCTRL  OMAP4_CLKCTRL_INDEX(0x30)
0087 #define OMAP4_HSI_CLKCTRL   OMAP4_CLKCTRL_INDEX(0x38)
0088 #define OMAP4_USB_HOST_HS_CLKCTRL   OMAP4_CLKCTRL_INDEX(0x58)
0089 #define OMAP4_USB_OTG_HS_CLKCTRL    OMAP4_CLKCTRL_INDEX(0x60)
0090 #define OMAP4_USB_TLL_HS_CLKCTRL    OMAP4_CLKCTRL_INDEX(0x68)
0091 #define OMAP4_USB_HOST_FS_CLKCTRL   OMAP4_CLKCTRL_INDEX(0xd0)
0092 #define OMAP4_OCP2SCP_USB_PHY_CLKCTRL   OMAP4_CLKCTRL_INDEX(0xe0)
0093
0094 /* l4_per clocks */
0095 #define OMAP4_TIMER10_CLKCTRL   OMAP4_CLKCTRL_INDEX(0x28)
0096 #define OMAP4_TIMER11_CLKCTRL   OMAP4_CLKCTRL_INDEX(0x30)
0097 #define OMAP4_TIMER2_CLKCTRL    OMAP4_CLKCTRL_INDEX(0x38)
0098 #define OMAP4_TIMER3_CLKCTRL    OMAP4_CLKCTRL_INDEX(0x40)
0099 #define OMAP4_TIMER4_CLKCTRL    OMAP4_CLKCTRL_INDEX(0x48)
0100 #define OMAP4_TIMER9_CLKCTRL    OMAP4_CLKCTRL_INDEX(0x50)
0101 #define OMAP4_ELM_CLKCTRL   OMAP4_CLKCTRL_INDEX(0x58)
0102 #define OMAP4_GPIO2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60)
0103 #define OMAP4_GPIO3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68)
0104 #define OMAP4_GPIO4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x70)
0105 #define OMAP4_GPIO5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78)
0106 #define OMAP4_GPIO6_CLKCTRL OMAP4_CLKCTRL_INDEX(0x80)
0107 #define OMAP4_HDQ1W_CLKCTRL OMAP4_CLKCTRL_INDEX(0x88)
0108 #define OMAP4_I2C1_CLKCTRL  OMAP4_CLKCTRL_INDEX(0xa0)
0109 #define OMAP4_I2C2_CLKCTRL  OMAP4_CLKCTRL_INDEX(0xa8)
0110 #define OMAP4_I2C3_CLKCTRL  OMAP4_CLKCTRL_INDEX(0xb0)
0111 #define OMAP4_I2C4_CLKCTRL  OMAP4_CLKCTRL_INDEX(0xb8)
0112 #define OMAP4_L4_PER_CLKCTRL    OMAP4_CLKCTRL_INDEX(0xc0)
0113 #define OMAP4_MCBSP4_CLKCTRL    OMAP4_CLKCTRL_INDEX(0xe0)
0114 #define OMAP4_MCSPI1_CLKCTRL    OMAP4_CLKCTRL_INDEX(0xf0)
0115 #define OMAP4_MCSPI2_CLKCTRL    OMAP4_CLKCTRL_INDEX(0xf8)
0116 #define OMAP4_MCSPI3_CLKCTRL    OMAP4_CLKCTRL_INDEX(0x100)
0117 #define OMAP4_MCSPI4_CLKCTRL    OMAP4_CLKCTRL_INDEX(0x108)
0118 #define OMAP4_MMC3_CLKCTRL  OMAP4_CLKCTRL_INDEX(0x120)
0119 #define OMAP4_MMC4_CLKCTRL  OMAP4_CLKCTRL_INDEX(0x128)
0120 #define OMAP4_SLIMBUS2_CLKCTRL  OMAP4_CLKCTRL_INDEX(0x138)
0121 #define OMAP4_UART1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x140)
0122 #define OMAP4_UART2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x148)
0123 #define OMAP4_UART3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x150)
0124 #define OMAP4_UART4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x158)
0125 #define OMAP4_MMC5_CLKCTRL  OMAP4_CLKCTRL_INDEX(0x160)
0126
0127 /* l4_secure clocks */
0128 #define OMAP4_L4_SECURE_CLKCTRL_OFFSET  0x1a0
0129 #define OMAP4_L4_SECURE_CLKCTRL_INDEX(offset)   ((offset) - OMAP4_L4_SECURE_CLKCTRL_OFFSET)
0130 #define OMAP4_AES1_CLKCTRL  OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a0)
0131 #define OMAP4_AES2_CLKCTRL  OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a8)
0132 #define OMAP4_DES3DES_CLKCTRL   OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b0)
0133 #define OMAP4_PKA_CLKCTRL   OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b8)
0134 #define OMAP4_RNG_CLKCTRL   OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c0)
0135 #define OMAP4_SHA2MD5_CLKCTRL   OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c8)
0136 #define OMAP4_CRYPTODMA_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1d8)
0137
0138 /* l4_wkup clocks */
0139 #define OMAP4_L4_WKUP_CLKCTRL   OMAP4_CLKCTRL_INDEX(0x20)
0140 #define OMAP4_WD_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
0141 #define OMAP4_GPIO1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
0142 #define OMAP4_TIMER1_CLKCTRL    OMAP4_CLKCTRL_INDEX(0x40)
0143 #define OMAP4_COUNTER_32K_CLKCTRL   OMAP4_CLKCTRL_INDEX(0x50)
0144 #define OMAP4_KBD_CLKCTRL   OMAP4_CLKCTRL_INDEX(0x78)
0145
0146 /* emu_sys clocks */
0147 #define OMAP4_DEBUGSS_CLKCTRL   OMAP4_CLKCTRL_INDEX(0x20)
0148
0149 #endif