dt-bindings/clock/nuvoton%2Cnpcm845-clk.h

0001 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
0002 /*
0003  * Copyright (C) 2021 Nuvoton Technologies.
0004  * Author: Tomer Maimon <tomer.maimon@nuvoton.com>
0005  *
0006  * Device Tree binding constants for NPCM8XX clock controller.
0007  */
0008
0009 #ifndef __DT_BINDINGS_CLOCK_NPCM8XX_H
0010 #define __DT_BINDINGS_CLOCK_NPCM8XX_H
0011
0012 #define NPCM8XX_CLK_CPU     0
0013 #define NPCM8XX_CLK_GFX_PIXEL   1
0014 #define NPCM8XX_CLK_MC      2
0015 #define NPCM8XX_CLK_ADC     3
0016 #define NPCM8XX_CLK_AHB     4
0017 #define NPCM8XX_CLK_TIMER   5
0018 #define NPCM8XX_CLK_UART    6
0019 #define NPCM8XX_CLK_UART2   7
0020 #define NPCM8XX_CLK_MMC     8
0021 #define NPCM8XX_CLK_SPI3    9
0022 #define NPCM8XX_CLK_PCI     10
0023 #define NPCM8XX_CLK_AXI     11
0024 #define NPCM8XX_CLK_APB4    12
0025 #define NPCM8XX_CLK_APB3    13
0026 #define NPCM8XX_CLK_APB2    14
0027 #define NPCM8XX_CLK_APB1    15
0028 #define NPCM8XX_CLK_APB5    16
0029 #define NPCM8XX_CLK_CLKOUT  17
0030 #define NPCM8XX_CLK_GFX     18
0031 #define NPCM8XX_CLK_SU      19
0032 #define NPCM8XX_CLK_SU48    20
0033 #define NPCM8XX_CLK_SDHC    21
0034 #define NPCM8XX_CLK_SPI0    22
0035 #define NPCM8XX_CLK_SPI1    23
0036 #define NPCM8XX_CLK_SPIX    24
0037 #define NPCM8XX_CLK_RG      25
0038 #define NPCM8XX_CLK_RCP     26
0039 #define NPCM8XX_CLK_PRE_ADC 27
0040 #define NPCM8XX_CLK_ATB     28
0041 #define NPCM8XX_CLK_PRE_CLK 29
0042 #define NPCM8XX_CLK_TH      30
0043 #define NPCM8XX_CLK_REFCLK  31
0044 #define NPCM8XX_CLK_SYSBYPCK    32
0045 #define NPCM8XX_CLK_MCBYPCK 33
0046
0047 #define NPCM8XX_NUM_CLOCKS  (NPCM8XX_CLK_MCBYPCK + 1)
0048
0049 #endif