dt-bindings/clock/mt8167-clk.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2020 MediaTek Inc.
0004  * Copyright (c) 2020 BayLibre, SAS.
0005  * Author: James Liao <jamesjj.liao@mediatek.com>
0006  *         Fabien Parent <fparent@baylibre.com>
0007  */
0008
0009 #ifndef _DT_BINDINGS_CLK_MT8167_H
0010 #define _DT_BINDINGS_CLK_MT8167_H
0011
0012 /* MT8167 is based on MT8516 */
0013 #include <dt-bindings/clock/mt8516-clk.h>
0014
0015 /* APMIXEDSYS */
0016
0017 #define CLK_APMIXED_TVDPLL      (CLK_APMIXED_NR_CLK + 0)
0018 #define CLK_APMIXED_LVDSPLL     (CLK_APMIXED_NR_CLK + 1)
0019 #define CLK_APMIXED_HDMI_REF        (CLK_APMIXED_NR_CLK + 2)
0020 #define MT8167_CLK_APMIXED_NR_CLK   (CLK_APMIXED_NR_CLK + 3)
0021
0022 /* TOPCKGEN */
0023
0024 #define CLK_TOP_DSI0_LNTC_DSICK     (CLK_TOP_NR_CLK + 0)
0025 #define CLK_TOP_VPLL_DPIX       (CLK_TOP_NR_CLK + 1)
0026 #define CLK_TOP_LVDSTX_CLKDIG_CTS   (CLK_TOP_NR_CLK + 2)
0027 #define CLK_TOP_HDMTX_CLKDIG_CTS    (CLK_TOP_NR_CLK + 3)
0028 #define CLK_TOP_LVDSPLL         (CLK_TOP_NR_CLK + 4)
0029 #define CLK_TOP_LVDSPLL_D2      (CLK_TOP_NR_CLK + 5)
0030 #define CLK_TOP_LVDSPLL_D4      (CLK_TOP_NR_CLK + 6)
0031 #define CLK_TOP_LVDSPLL_D8      (CLK_TOP_NR_CLK + 7)
0032 #define CLK_TOP_MIPI_26M        (CLK_TOP_NR_CLK + 8)
0033 #define CLK_TOP_TVDPLL          (CLK_TOP_NR_CLK + 9)
0034 #define CLK_TOP_TVDPLL_D2       (CLK_TOP_NR_CLK + 10)
0035 #define CLK_TOP_TVDPLL_D4       (CLK_TOP_NR_CLK + 11)
0036 #define CLK_TOP_TVDPLL_D8       (CLK_TOP_NR_CLK + 12)
0037 #define CLK_TOP_TVDPLL_D16      (CLK_TOP_NR_CLK + 13)
0038 #define CLK_TOP_PWM_MM          (CLK_TOP_NR_CLK + 14)
0039 #define CLK_TOP_CAM_MM          (CLK_TOP_NR_CLK + 15)
0040 #define CLK_TOP_MFG_MM          (CLK_TOP_NR_CLK + 16)
0041 #define CLK_TOP_SPM_52M         (CLK_TOP_NR_CLK + 17)
0042 #define CLK_TOP_MIPI_26M_DBG        (CLK_TOP_NR_CLK + 18)
0043 #define CLK_TOP_SCAM_MM         (CLK_TOP_NR_CLK + 19)
0044 #define CLK_TOP_SMI_MM          (CLK_TOP_NR_CLK + 20)
0045 #define CLK_TOP_26M_HDMI_SIFM       (CLK_TOP_NR_CLK + 21)
0046 #define CLK_TOP_26M_CEC         (CLK_TOP_NR_CLK + 22)
0047 #define CLK_TOP_32K_CEC         (CLK_TOP_NR_CLK + 23)
0048 #define CLK_TOP_GCPU_B          (CLK_TOP_NR_CLK + 24)
0049 #define CLK_TOP_RG_VDEC         (CLK_TOP_NR_CLK + 25)
0050 #define CLK_TOP_RG_FDPI0        (CLK_TOP_NR_CLK + 26)
0051 #define CLK_TOP_RG_FDPI1        (CLK_TOP_NR_CLK + 27)
0052 #define CLK_TOP_RG_AXI_MFG      (CLK_TOP_NR_CLK + 28)
0053 #define CLK_TOP_RG_SLOW_MFG     (CLK_TOP_NR_CLK + 29)
0054 #define CLK_TOP_GFMUX_EMI1X_SEL     (CLK_TOP_NR_CLK + 30)
0055 #define CLK_TOP_CSW_MUX_MFG_SEL     (CLK_TOP_NR_CLK + 31)
0056 #define CLK_TOP_CAMTG_MM_SEL        (CLK_TOP_NR_CLK + 32)
0057 #define CLK_TOP_PWM_MM_SEL      (CLK_TOP_NR_CLK + 33)
0058 #define CLK_TOP_SPM_52M_SEL     (CLK_TOP_NR_CLK + 34)
0059 #define CLK_TOP_MFG_MM_SEL      (CLK_TOP_NR_CLK + 35)
0060 #define CLK_TOP_SMI_MM_SEL      (CLK_TOP_NR_CLK + 36)
0061 #define CLK_TOP_SCAM_MM_SEL     (CLK_TOP_NR_CLK + 37)
0062 #define CLK_TOP_VDEC_MM_SEL     (CLK_TOP_NR_CLK + 38)
0063 #define CLK_TOP_DPI0_MM_SEL     (CLK_TOP_NR_CLK + 39)
0064 #define CLK_TOP_DPI1_MM_SEL     (CLK_TOP_NR_CLK + 40)
0065 #define CLK_TOP_AXI_MFG_IN_SEL      (CLK_TOP_NR_CLK + 41)
0066 #define CLK_TOP_SLOW_MFG_SEL        (CLK_TOP_NR_CLK + 42)
0067 #define MT8167_CLK_TOP_NR_CLK       (CLK_TOP_NR_CLK + 43)
0068
0069 /* MFGCFG */
0070
0071 #define CLK_MFG_BAXI            0
0072 #define CLK_MFG_BMEM            1
0073 #define CLK_MFG_BG3D            2
0074 #define CLK_MFG_B26M            3
0075 #define CLK_MFG_NR_CLK          4
0076
0077 /* MMSYS */
0078
0079 #define CLK_MM_SMI_COMMON       0
0080 #define CLK_MM_SMI_LARB0        1
0081 #define CLK_MM_CAM_MDP          2
0082 #define CLK_MM_MDP_RDMA         3
0083 #define CLK_MM_MDP_RSZ0         4
0084 #define CLK_MM_MDP_RSZ1         5
0085 #define CLK_MM_MDP_TDSHP        6
0086 #define CLK_MM_MDP_WDMA         7
0087 #define CLK_MM_MDP_WROT         8
0088 #define CLK_MM_FAKE_ENG         9
0089 #define CLK_MM_DISP_OVL0        10
0090 #define CLK_MM_DISP_RDMA0       11
0091 #define CLK_MM_DISP_RDMA1       12
0092 #define CLK_MM_DISP_WDMA        13
0093 #define CLK_MM_DISP_COLOR       14
0094 #define CLK_MM_DISP_CCORR       15
0095 #define CLK_MM_DISP_AAL         16
0096 #define CLK_MM_DISP_GAMMA       17
0097 #define CLK_MM_DISP_DITHER      18
0098 #define CLK_MM_DISP_UFOE        19
0099 #define CLK_MM_DISP_PWM_MM      20
0100 #define CLK_MM_DISP_PWM_26M     21
0101 #define CLK_MM_DSI_ENGINE       22
0102 #define CLK_MM_DSI_DIGITAL      23
0103 #define CLK_MM_DPI0_ENGINE      24
0104 #define CLK_MM_DPI0_PXL         25
0105 #define CLK_MM_LVDS_PXL         26
0106 #define CLK_MM_LVDS_CTS         27
0107 #define CLK_MM_DPI1_ENGINE      28
0108 #define CLK_MM_DPI1_PXL         29
0109 #define CLK_MM_HDMI_PXL         30
0110 #define CLK_MM_HDMI_SPDIF       31
0111 #define CLK_MM_HDMI_ADSP_BCK        32
0112 #define CLK_MM_HDMI_PLL         33
0113 #define CLK_MM_NR_CLK           34
0114
0115 /* IMGSYS */
0116
0117 #define CLK_IMG_LARB1_SMI       0
0118 #define CLK_IMG_CAM_SMI         1
0119 #define CLK_IMG_CAM_CAM         2
0120 #define CLK_IMG_SEN_TG          3
0121 #define CLK_IMG_SEN_CAM         4
0122 #define CLK_IMG_VENC            5
0123 #define CLK_IMG_NR_CLK          6
0124
0125 /* VDECSYS */
0126
0127 #define CLK_VDEC_CKEN           0
0128 #define CLK_VDEC_LARB1_CKEN     1
0129 #define CLK_VDEC_NR_CLK         2
0130
0131 #endif /* _DT_BINDINGS_CLK_MT8167_H */