dt-bindings/clock/microchip%2Cmpfs-clock.h

0001 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
0002 /*
0003  * Daire McNamara,<daire.mcnamara@microchip.com>
0004  * Copyright (C) 2020-2022 Microchip Technology Inc.  All rights reserved.
0005  */
0006
0007 #ifndef _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_
0008 #define _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_
0009
0010 #define CLK_CPU     0
0011 #define CLK_AXI     1
0012 #define CLK_AHB     2
0013
0014 #define CLK_ENVM    3
0015 #define CLK_MAC0    4
0016 #define CLK_MAC1    5
0017 #define CLK_MMC     6
0018 #define CLK_TIMER   7
0019 #define CLK_MMUART0 8
0020 #define CLK_MMUART1 9
0021 #define CLK_MMUART2 10
0022 #define CLK_MMUART3 11
0023 #define CLK_MMUART4 12
0024 #define CLK_SPI0    13
0025 #define CLK_SPI1    14
0026 #define CLK_I2C0    15
0027 #define CLK_I2C1    16
0028 #define CLK_CAN0    17
0029 #define CLK_CAN1    18
0030 #define CLK_USB     19
0031 #define CLK_RESERVED    20
0032 #define CLK_RTC     21
0033 #define CLK_QSPI    22
0034 #define CLK_GPIO0   23
0035 #define CLK_GPIO1   24
0036 #define CLK_GPIO2   25
0037 #define CLK_DDRC    26
0038 #define CLK_FIC0    27
0039 #define CLK_FIC1    28
0040 #define CLK_FIC2    29
0041 #define CLK_FIC3    30
0042 #define CLK_ATHENA  31
0043 #define CLK_CFM     32
0044
0045 #define CLK_RTCREF  33
0046 #define CLK_MSSPLL  34
0047
0048 #endif  /* _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ */