dt-bindings/clock/marvell%2Cpxa168.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __DTS_MARVELL_PXA168_CLOCK_H
0003 #define __DTS_MARVELL_PXA168_CLOCK_H
0004
0005 /* fixed clocks and plls */
0006 #define PXA168_CLK_CLK32        1
0007 #define PXA168_CLK_VCTCXO       2
0008 #define PXA168_CLK_PLL1         3
0009 #define PXA168_CLK_PLL1_2       8
0010 #define PXA168_CLK_PLL1_4       9
0011 #define PXA168_CLK_PLL1_8       10
0012 #define PXA168_CLK_PLL1_16      11
0013 #define PXA168_CLK_PLL1_6       12
0014 #define PXA168_CLK_PLL1_12      13
0015 #define PXA168_CLK_PLL1_24      14
0016 #define PXA168_CLK_PLL1_48      15
0017 #define PXA168_CLK_PLL1_96      16
0018 #define PXA168_CLK_PLL1_13      17
0019 #define PXA168_CLK_PLL1_13_1_5      18
0020 #define PXA168_CLK_PLL1_2_1_5       19
0021 #define PXA168_CLK_PLL1_3_16        20
0022 #define PXA168_CLK_PLL1_192     21
0023 #define PXA168_CLK_UART_PLL     27
0024 #define PXA168_CLK_USB_PLL      28
0025
0026 /* apb peripherals */
0027 #define PXA168_CLK_TWSI0        60
0028 #define PXA168_CLK_TWSI1        61
0029 #define PXA168_CLK_TWSI2        62
0030 #define PXA168_CLK_TWSI3        63
0031 #define PXA168_CLK_GPIO         64
0032 #define PXA168_CLK_KPC          65
0033 #define PXA168_CLK_RTC          66
0034 #define PXA168_CLK_PWM0         67
0035 #define PXA168_CLK_PWM1         68
0036 #define PXA168_CLK_PWM2         69
0037 #define PXA168_CLK_PWM3         70
0038 #define PXA168_CLK_UART0        71
0039 #define PXA168_CLK_UART1        72
0040 #define PXA168_CLK_UART2        73
0041 #define PXA168_CLK_SSP0         74
0042 #define PXA168_CLK_SSP1         75
0043 #define PXA168_CLK_SSP2         76
0044 #define PXA168_CLK_SSP3         77
0045 #define PXA168_CLK_SSP4         78
0046 #define PXA168_CLK_TIMER        79
0047
0048 /* axi peripherals */
0049 #define PXA168_CLK_DFC          100
0050 #define PXA168_CLK_SDH0         101
0051 #define PXA168_CLK_SDH1         102
0052 #define PXA168_CLK_SDH2         103
0053 #define PXA168_CLK_USB          104
0054 #define PXA168_CLK_SPH          105
0055 #define PXA168_CLK_DISP0        106
0056 #define PXA168_CLK_CCIC0        107
0057 #define PXA168_CLK_CCIC0_PHY        108
0058 #define PXA168_CLK_CCIC0_SPHY       109
0059
0060 #define PXA168_NR_CLKS          200
0061 #endif