dt-bindings/clock/marvell%2Cmmp2.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __DTS_MARVELL_MMP2_CLOCK_H
0003 #define __DTS_MARVELL_MMP2_CLOCK_H
0004
0005 /* fixed clocks and plls */
0006 #define MMP2_CLK_CLK32          1
0007 #define MMP2_CLK_VCTCXO         2
0008 #define MMP2_CLK_PLL1           3
0009 #define MMP2_CLK_PLL1_2         8
0010 #define MMP2_CLK_PLL1_4         9
0011 #define MMP2_CLK_PLL1_8         10
0012 #define MMP2_CLK_PLL1_16        11
0013 #define MMP2_CLK_PLL1_3         12
0014 #define MMP2_CLK_PLL1_6         13
0015 #define MMP2_CLK_PLL1_12        14
0016 #define MMP2_CLK_PLL1_20        15
0017 #define MMP2_CLK_PLL2           16
0018 #define MMP2_CLK_PLL2_2         17
0019 #define MMP2_CLK_PLL2_4         18
0020 #define MMP2_CLK_PLL2_8         19
0021 #define MMP2_CLK_PLL2_16        20
0022 #define MMP2_CLK_PLL2_3         21
0023 #define MMP2_CLK_PLL2_6         22
0024 #define MMP2_CLK_PLL2_12        23
0025 #define MMP2_CLK_VCTCXO_2       24
0026 #define MMP2_CLK_VCTCXO_4       25
0027 #define MMP2_CLK_UART_PLL       26
0028 #define MMP2_CLK_USB_PLL        27
0029 #define MMP3_CLK_PLL1_P         28
0030 #define MMP3_CLK_PLL2_P         29
0031 #define MMP3_CLK_PLL3           30
0032 #define MMP2_CLK_I2S0           31
0033 #define MMP2_CLK_I2S1           32
0034
0035 /* apb peripherals */
0036 #define MMP2_CLK_TWSI0          60
0037 #define MMP2_CLK_TWSI1          61
0038 #define MMP2_CLK_TWSI2          62
0039 #define MMP2_CLK_TWSI3          63
0040 #define MMP2_CLK_TWSI4          64
0041 #define MMP2_CLK_TWSI5          65
0042 #define MMP2_CLK_GPIO           66
0043 #define MMP2_CLK_KPC            67
0044 #define MMP2_CLK_RTC            68
0045 #define MMP2_CLK_PWM0           69
0046 #define MMP2_CLK_PWM1           70
0047 #define MMP2_CLK_PWM2           71
0048 #define MMP2_CLK_PWM3           72
0049 #define MMP2_CLK_UART0          73
0050 #define MMP2_CLK_UART1          74
0051 #define MMP2_CLK_UART2          75
0052 #define MMP2_CLK_UART3          76
0053 #define MMP2_CLK_SSP0           77
0054 #define MMP2_CLK_SSP1           78
0055 #define MMP2_CLK_SSP2           79
0056 #define MMP2_CLK_SSP3           80
0057 #define MMP2_CLK_TIMER          81
0058 #define MMP2_CLK_THERMAL0       82
0059 #define MMP3_CLK_THERMAL1       83
0060 #define MMP3_CLK_THERMAL2       84
0061 #define MMP3_CLK_THERMAL3       85
0062
0063 /* axi peripherals */
0064 #define MMP2_CLK_SDH0           101
0065 #define MMP2_CLK_SDH1           102
0066 #define MMP2_CLK_SDH2           103
0067 #define MMP2_CLK_SDH3           104
0068 #define MMP2_CLK_USB            105
0069 #define MMP2_CLK_DISP0          106
0070 #define MMP2_CLK_DISP0_MUX      107
0071 #define MMP2_CLK_DISP0_SPHY     108
0072 #define MMP2_CLK_DISP1          109
0073 #define MMP2_CLK_DISP1_MUX      110
0074 #define MMP2_CLK_CCIC_ARBITER       111
0075 #define MMP2_CLK_CCIC0          112
0076 #define MMP2_CLK_CCIC0_MIX      113
0077 #define MMP2_CLK_CCIC0_PHY      114
0078 #define MMP2_CLK_CCIC0_SPHY     115
0079 #define MMP2_CLK_CCIC1          116
0080 #define MMP2_CLK_CCIC1_MIX      117
0081 #define MMP2_CLK_CCIC1_PHY      118
0082 #define MMP2_CLK_CCIC1_SPHY     119
0083 #define MMP2_CLK_DISP0_LCDC     120
0084 #define MMP2_CLK_USBHSIC0       121
0085 #define MMP2_CLK_USBHSIC1       122
0086 #define MMP2_CLK_GPU_BUS        123
0087 #define MMP3_CLK_GPU_BUS        MMP2_CLK_GPU_BUS
0088 #define MMP2_CLK_GPU_3D         124
0089 #define MMP3_CLK_GPU_3D         MMP2_CLK_GPU_3D
0090 #define MMP3_CLK_GPU_2D         125
0091 #define MMP3_CLK_SDH4           126
0092 #define MMP2_CLK_AUDIO          127
0093
0094 #define MMP2_NR_CLKS            200
0095 #endif