dt-bindings/clock/lpc18xx-ccu.h

0001 /*
0002  * Copyright (c) 2015 Joachim Eastwood <manabian@gmail.com>
0003  *
0004  * This code is released using a dual license strategy: BSD/GPL
0005  * You can choose the licence that better fits your requirements.
0006  *
0007  * Released under the terms of 3-clause BSD License
0008  * Released under the terms of GNU General Public License Version 2.0
0009  *
0010  */
0011
0012 /* Clock Control Unit 1 (CCU1) clock offsets */
0013 #define CLK_APB3_BUS        0x100
0014 #define CLK_APB3_I2C1       0x108
0015 #define CLK_APB3_DAC        0x110
0016 #define CLK_APB3_ADC0       0x118
0017 #define CLK_APB3_ADC1       0x120
0018 #define CLK_APB3_CAN0       0x128
0019 #define CLK_APB1_BUS        0x200
0020 #define CLK_APB1_MOTOCON_PWM    0x208
0021 #define CLK_APB1_I2C0       0x210
0022 #define CLK_APB1_I2S        0x218
0023 #define CLK_APB1_CAN1       0x220
0024 #define CLK_SPIFI       0x300
0025 #define CLK_CPU_BUS     0x400
0026 #define CLK_CPU_SPIFI       0x408
0027 #define CLK_CPU_GPIO        0x410
0028 #define CLK_CPU_LCD     0x418
0029 #define CLK_CPU_ETHERNET    0x420
0030 #define CLK_CPU_USB0        0x428
0031 #define CLK_CPU_EMC     0x430
0032 #define CLK_CPU_SDIO        0x438
0033 #define CLK_CPU_DMA     0x440
0034 #define CLK_CPU_CORE        0x448
0035 #define CLK_CPU_SCT     0x468
0036 #define CLK_CPU_USB1        0x470
0037 #define CLK_CPU_EMCDIV      0x478
0038 #define CLK_CPU_FLASHA      0x480
0039 #define CLK_CPU_FLASHB      0x488
0040 #define CLK_CPU_M0APP       0x490
0041 #define CLK_CPU_ADCHS       0x498
0042 #define CLK_CPU_EEPROM      0x4a0
0043 #define CLK_CPU_WWDT        0x500
0044 #define CLK_CPU_UART0       0x508
0045 #define CLK_CPU_UART1       0x510
0046 #define CLK_CPU_SSP0        0x518
0047 #define CLK_CPU_TIMER0      0x520
0048 #define CLK_CPU_TIMER1      0x528
0049 #define CLK_CPU_SCU     0x530
0050 #define CLK_CPU_CREG        0x538
0051 #define CLK_CPU_RITIMER     0x600
0052 #define CLK_CPU_UART2       0x608
0053 #define CLK_CPU_UART3       0x610
0054 #define CLK_CPU_TIMER2      0x618
0055 #define CLK_CPU_TIMER3      0x620
0056 #define CLK_CPU_SSP1        0x628
0057 #define CLK_CPU_QEI     0x630
0058 #define CLK_PERIPH_BUS      0x700
0059 #define CLK_PERIPH_CORE     0x710
0060 #define CLK_PERIPH_SGPIO    0x718
0061 #define CLK_USB0        0x800
0062 #define CLK_USB1        0x900
0063 #define CLK_SPI         0xA00
0064 #define CLK_ADCHS       0xB00
0065
0066 /* Clock Control Unit 2 (CCU2) clock offsets */
0067 #define CLK_AUDIO       0x100
0068 #define CLK_APB2_UART3      0x200
0069 #define CLK_APB2_UART2      0x300
0070 #define CLK_APB0_UART1      0x400
0071 #define CLK_APB0_UART0      0x500
0072 #define CLK_APB2_SSP1       0x600
0073 #define CLK_APB0_SSP0       0x700
0074 #define CLK_SDIO        0x800