dt-bindings/clock/k210-clk.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
0004  * Copyright (c) 2020 Western Digital Corporation or its affiliates.
0005  */
0006 #ifndef CLOCK_K210_CLK_H
0007 #define CLOCK_K210_CLK_H
0008
0009 /*
0010  * Kendryte K210 SoC clock identifiers (arbitrary values).
0011  */
0012 #define K210_CLK_CPU    0
0013 #define K210_CLK_SRAM0  1
0014 #define K210_CLK_SRAM1  2
0015 #define K210_CLK_AI 3
0016 #define K210_CLK_DMA    4
0017 #define K210_CLK_FFT    5
0018 #define K210_CLK_ROM    6
0019 #define K210_CLK_DVP    7
0020 #define K210_CLK_APB0   8
0021 #define K210_CLK_APB1   9
0022 #define K210_CLK_APB2   10
0023 #define K210_CLK_I2S0   11
0024 #define K210_CLK_I2S1   12
0025 #define K210_CLK_I2S2   13
0026 #define K210_CLK_I2S0_M 14
0027 #define K210_CLK_I2S1_M 15
0028 #define K210_CLK_I2S2_M 16
0029 #define K210_CLK_WDT0   17
0030 #define K210_CLK_WDT1   18
0031 #define K210_CLK_SPI0   19
0032 #define K210_CLK_SPI1   20
0033 #define K210_CLK_SPI2   21
0034 #define K210_CLK_I2C0   22
0035 #define K210_CLK_I2C1   23
0036 #define K210_CLK_I2C2   24
0037 #define K210_CLK_SPI3   25
0038 #define K210_CLK_TIMER0 26
0039 #define K210_CLK_TIMER1 27
0040 #define K210_CLK_TIMER2 28
0041 #define K210_CLK_GPIO   29
0042 #define K210_CLK_UART1  30
0043 #define K210_CLK_UART2  31
0044 #define K210_CLK_UART3  32
0045 #define K210_CLK_FPIOA  33
0046 #define K210_CLK_SHA    34
0047 #define K210_CLK_AES    35
0048 #define K210_CLK_OTP    36
0049 #define K210_CLK_RTC    37
0050
0051 #define K210_NUM_CLKS   38
0052
0053 #endif /* CLOCK_K210_CLK_H */