dt-bindings/clock/ingenic%2Cx1830-cgu.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * This header provides clock numbers for the ingenic,x1830-cgu DT binding.
0004  *
0005  * They are roughly ordered as:
0006  *   - external clocks
0007  *   - PLLs
0008  *   - muxes/dividers in the order they appear in the x1830 programmers manual
0009  *   - gates in order of their bit in the CLKGR* registers
0010  */
0011
0012 #ifndef __DT_BINDINGS_CLOCK_X1830_CGU_H__
0013 #define __DT_BINDINGS_CLOCK_X1830_CGU_H__
0014
0015 #define X1830_CLK_EXCLK         0
0016 #define X1830_CLK_RTCLK         1
0017 #define X1830_CLK_APLL          2
0018 #define X1830_CLK_MPLL          3
0019 #define X1830_CLK_EPLL          4
0020 #define X1830_CLK_VPLL          5
0021 #define X1830_CLK_OTGPHY        6
0022 #define X1830_CLK_SCLKA         7
0023 #define X1830_CLK_CPUMUX        8
0024 #define X1830_CLK_CPU           9
0025 #define X1830_CLK_L2CACHE       10
0026 #define X1830_CLK_AHB0          11
0027 #define X1830_CLK_AHB2PMUX      12
0028 #define X1830_CLK_AHB2          13
0029 #define X1830_CLK_PCLK          14
0030 #define X1830_CLK_DDR           15
0031 #define X1830_CLK_MAC           16
0032 #define X1830_CLK_LCD           17
0033 #define X1830_CLK_MSCMUX        18
0034 #define X1830_CLK_MSC0          19
0035 #define X1830_CLK_MSC1          20
0036 #define X1830_CLK_SSIPLL        21
0037 #define X1830_CLK_SSIPLL_DIV2   22
0038 #define X1830_CLK_SSIMUX        23
0039 #define X1830_CLK_EMC           24
0040 #define X1830_CLK_EFUSE         25
0041 #define X1830_CLK_OTG           26
0042 #define X1830_CLK_SSI0          27
0043 #define X1830_CLK_SMB0          28
0044 #define X1830_CLK_SMB1          29
0045 #define X1830_CLK_SMB2          30
0046 #define X1830_CLK_UART0         31
0047 #define X1830_CLK_UART1         32
0048 #define X1830_CLK_SSI1          33
0049 #define X1830_CLK_SFC           34
0050 #define X1830_CLK_PDMA          35
0051 #define X1830_CLK_TCU           36
0052 #define X1830_CLK_DTRNG         37
0053 #define X1830_CLK_OST           38
0054 #define X1830_CLK_EXCLK_DIV512  39
0055 #define X1830_CLK_RTC           40
0056
0057 #endif /* __DT_BINDINGS_CLOCK_X1830_CGU_H__ */